Re: JITs and 52-bit VA

2016-04-28 Thread Edward Nevill
FWIW: OpenJDK assumes 48 bit virtual address. There is no inherent reason for this other than we do movz/movk/movk to form an address. It is relatively trivial to change this to movz/movk/movk/movk All the best, Ed. On 28 April 2016 at 14:00, Maxim Kuvyrkov wrote: > This is a summary of dis

Re: Help with some assembler syntax

2015-12-07 Thread Edward Nevill
>> adrp Xn, dest >> add Xn, Xn, :lo12:dest >> blr Xn >> > > I don't suppose the branch predictor would like that very much, > though. Can't you keep the original arrangement, and use this sequence > instead? Or use the new sequence unconditionally, but nop out the add > instruction and change

Re: Help with some assembler syntax

2015-12-07 Thread Edward Nevill
> adrp, x0, dest > add x0, x0, #:lo12:dest Thanks! Thats the syntax I wanted. The use case is I want to benchmark this as a way of generating far calls, for use within the JIT for when code cache becomes > 128m. At the moment we generate trampolines tramp: ldr Xn, here br Xn here .dword d

Help with some assembler syntax

2015-12-07 Thread Edward Nevill
Hi, Does anyone know how I do adrp x0, dest & ~0xfff add x0, x0, dest & 0xfff in aarch64 assembler? Thanks for your help, Ed. ___ linaro-dev mailing list linaro-dev@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-dev

Re: can I flush the icache on armv8 from user mode

2014-08-29 Thread Edward Nevill
IALLUIS is not EL0. Regards, Ed. On Fri, 2014-08-29 at 13:52 +0200, Ard Biesheuvel wrote: > On 29 August 2014 13:02, Edward Nevill wrote: > > We have a need on OpenJDK to flush the entire icache. Basically this > > need occurs when we do a garbage collection which may

can I flush the icache on armv8 from user mode

2014-08-29 Thread Edward Nevill
Hi, We have a need on OpenJDK to flush the entire icache. Basically this need occurs when we do a garbage collection which may include garbage collection and patching of the dynamically generated code. Problem is, the IC IALLUIS instruction which we need is only executable from EL1 or greater. I

Re: detecting long multiply overflow

2014-07-04 Thread Edward Nevill
On Fri, 2014-07-04 at 18:17 +0200, Ard Biesheuvel wrote: > On 4 July 2014 18:13, Edward Nevill wrote: > If you are saying AArch64, I am assuming you can use inline asm and umulh, no? > Thank you, thank you, thank you, You just saved me some very messy c

detecting long multiply overflow

2014-07-04 Thread Edward Nevill
Hi, Does anyone know of a nice way to detect 64 x 64 -> 64 multiply overflow on aarch64? On x86 you can just use the V flag, but aarch64 seems to have no option to set the flags after a MUL instruction which I find very odd. The only solution I can think of is to do the equivalent of r = a