On 20/11/2020 13:39, Adhemerval Zanella wrote:
>
>
> On 19/11/2020 12:43, David Brown wrote:
>> I'm not aware of anyone working on it. It might be worthwhile to at least
>> create a github issue for it (there is one for RISC-V). The code generator
>> in Chez i
On 19/11/2020 12:43, David Brown wrote:
> I'm not aware of anyone working on it. It might be worthwhile to at least
> create a github issue for it (there is one for RISC-V). The code generator in
> Chez is fairly custom, but there are a lot of similarities between aarch32
> and aarch64, so it
Hi all,
Is anyone working on a aarch64 port to the project [1]?
https://github.com/cisco/ChezScheme
Thanks.
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On 26/11/2018 16:58, Wookey wrote:
> On 2018-11-26 09:08 -0600, Tom Gall wrote:
>> On Mon, Nov 26, 2018 at 8:46 AM Steve McIntyre
>> wrote:
>>>
>>> Quite. This is exactly the tension behind the dicussion - while arm64
>>> machines are mainly mobile so far, we're finally starting to see
>>> bigge
I do not think this issue is inherent to all JIT implements, but rather to
luajit with its NaN-tagging scheme [1] which packs different types of objects
in a 8-byte. It works well with x86_64 that limits the VMA to 47-bits, but
things get messy with large VMA support. Luajit work around this issue
