Quoting Richard Zhao (2013-03-03 05:27:52)
> Hi Mike,
>
> On Sun, Mar 03, 2013 at 02:54:24AM -0800, Mike Turquette wrote:
> > Quoting Richard Zhao (2013-03-02 00:22:19)
> > > On Fri, Mar 01, 2013 at 06:55:54PM -0800, Bill Huang wrote:
> > > > On Sat, 2013-03-02 at 04:48 +0800, Mike Turquette wrote
On Thu, Feb 14, 2013 at 05:07:43PM +, Jon Medhurst (Tixy) wrote:
The function v7_coherent_kern_range uses the macro icache_line_size to
read the current CPUs icache line size for the purpose of invalidating
all cache lines in the given range.
Unfortunately, on the TC2 big.LITTLE test chip,
Hi Mike,
On Sun, Mar 03, 2013 at 02:54:24AM -0800, Mike Turquette wrote:
> Quoting Richard Zhao (2013-03-02 00:22:19)
> > On Fri, Mar 01, 2013 at 06:55:54PM -0800, Bill Huang wrote:
> > > On Sat, 2013-03-02 at 04:48 +0800, Mike Turquette wrote:
> > > > Quoting Mike Turquette (2013-03-01 10:22:34)
Quoting Richard Zhao (2013-03-02 00:22:19)
> On Fri, Mar 01, 2013 at 06:55:54PM -0800, Bill Huang wrote:
> > On Sat, 2013-03-02 at 04:48 +0800, Mike Turquette wrote:
> > > Quoting Mike Turquette (2013-03-01 10:22:34)
> > > > Quoting Bill Huang (2013-03-01 01:41:31)
> > > > > On Thu, 2013-02-28 at 1