commit 67ee3dd (mx53: Make PLL2 to be the parent of UART clock)
changed UART parent from PLL3 to PLL2.
Do not reconfigure PLL2 in order to avoid a messed up console output.
Signed-off-by: Fabio Estevam
---
This applies against Linaro-u-boot-2012.04.2
arch/arm/cpu/armv7/mx5/clock.c |9
Daniel Lezcano writes:
> On 04/24/2012 04:05 PM, Daniel Lezcano wrote:
>> This patchset makes some cleanup on these cpuidle drivers
>> and consolidate the code across both architecture.
>>
>> Tested on OMAP3 (igepV2).
>> Partially tested on OMAP4 (pandaboard), without offlining the cpu1.
Without
On Wed, Apr 25, 2012 at 10:00 AM, Enric Balletbò i Serra
wrote:
> 2012/4/4 Javier Martinez Canillas :
>> IGEP-based boards can have two different flash memories, a OneNAND or
>> a NAND device. The boot configuration pins (sys_boot) are used to
>> specify which memory is available.
>>
>> Also, this
On Wed, Apr 25, 2012 at 9:44 AM, Daniel Lezcano
wrote:
> On 04/25/2012 02:11 PM, Amit Daniel Kachhap wrote:
>>
>> This patch enables core cpuidle timekeeping and irq enabling and
>> remove those redundant parts from the exynos cpuidle drivers
>>
>> CC: Daniel Lezcano
>> CC: Robert Lee
>> Signed-of
Quantal is now open for development, with syncs from unstable starting shortly.
The development version starts with updated versions of GCC and OpenJDK, some
soname changes (boost, hdf5), and some changes with setting the build flags for
package builds. We are finally targeting Python3 as the
only
