[PATCH v3 10/20] KVM: ARM64: Add reset and access handlers for PMCCNTR register

Since the reset value of PMCCNTR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate reading to PMCCNTR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 17 +++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/arch

[PATCH v3 06/20] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register

Add reset handler which gets host value of PMCEID0 or PMCEID1. Since write action to PMCEID0 or PMCEID1 is ignored, add a new case for this. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 29 + 1 file changed, 25 insertions(+), 4 deletions(-) diff --git

[PATCH v3 14/20] KVM: ARM64: Add reset and access handlers for PMUSERENR register

The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown. While the reset value of PMUSERENR is zero, use reset_val_cp15 with zero for its reset handler. Add a helper for CP15 registers reset to specified value. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 5 +++-- arch

[PATCH v3 13/20] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register

Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMOVSSET or PMOVSCLR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 33 ++--- 1 file changed, 30 insertions

[PATCH v3 11/20] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register

perf_event_disable to disable the perf event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 46 + include/kvm/arm_pmu.h | 4 virt/kvm/arm/pmu.c| 48 +++ 3 files changed, 94 insertions(+), 4

[PATCH v3 12/20] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register

Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMINTENSET or PMINTENCLR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 34 ++ 1 file changed, 30

[PATCH v3 17/20] KVM: ARM64: Add PMU overflow interrupt routing

When calling perf_event_create_kernel_counter to create perf_event, assign a overflow handler. Then when perf event overflows, set irq_pending and call kvm_vcpu_kick() to sync the interrupt. Signed-off-by: Shannon Zhao --- arch/arm/kvm/arm.c| 4 include/kvm/arm_pmu.h | 2 ++ virt/kvm

[PATCH v3 18/20] KVM: ARM64: Reset PMU state when resetting vcpu

Signed-off-by: Shannon Zhao --- arch/arm64/kvm/reset.c | 3 +++ include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c | 18 ++ 3 files changed, 23 insertions(+) diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 91cf535..4da7f6c 100644 --- a/arch/arm64/kvm

[PATCH v3 20/20] KVM: ARM64: Add a new kvm ARM PMU device

Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement the kvm_device_ops for it. Signed-off-by: Shannon Zhao --- Documentation/virtual/kvm/devices/arm-pmu.txt | 15 + arch/arm64/include/uapi/asm/kvm.h | 3 + include/linux/kvm_host.h | 1

[PATCH v3 15/20] KVM: ARM64: Add reset and access handlers for PMSWINC register

Add access handler which emulates writing and reading PMSWINC register and add support for creating software increment event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 18 +- include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c| 33

[PATCH v3 19/20] KVM: ARM64: Free perf event of PMU when destroying vcpu

When KVM frees VCPU, it needs to free the perf_event of PMU. Signed-off-by: Shannon Zhao --- arch/arm/kvm/arm.c| 1 + include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c| 21 + 3 files changed, 24 insertions(+) diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c

[PATCH v3 16/20] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register

Add access handler which emulates writing and reading PMEVCNTRn and PMEVTYPERn. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 164 ++ 1 file changed, 164 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c

Re: [PATCH v3 04/20] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

On 2015/10/16 13:35, Wei Huang wrote: > > On 09/24/2015 05:31 PM, Shannon Zhao wrote: >> > Add reset handler which gets host value of PMCR_EL0 and make writable >> > bits architecturally UNKNOWN. Add a common access handler for PMU >> > registers which emulates

Re: [PATCH v3 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

On 2015/10/16 14:08, Wei Huang wrote: >> +/** >> > + * kvm_pmu_get_counter_value - get PMU counter value >> > + * @vcpu: The vcpu pointer >> > + * @select_idx: The counter index >> > + */ >> > +unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 >> > select_idx) >> > +{ >> > + u6

Re: [PATCH v3 10/20] KVM: ARM64: Add reset and access handlers for PMCCNTR register

On 2015/10/16 23:06, Wei Huang wrote: > > > On 09/24/2015 05:31 PM, Shannon Zhao wrote: >> Since the reset value of PMCCNTR is UNKNOWN, use reset_unknown for its >> reset handler. Add a new case to emulate reading to PMCCNTR register. >> >> Signed-off-by: Sh

Re: [PATCH v3 15/20] KVM: ARM64: Add reset and access handlers for PMSWINC register

On 2015/10/16 23:25, Wei Huang wrote: >> /** >> > + * kvm_pmu_software_increment - do software increment >> > + * @vcpu: The vcpu pointer >> > + * @val: the value guest writes to PMSWINC register >> > + */ >> > +void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val) >> > +{ >> > + int

Re: [PATCH v3 00/20] KVM: ARM64: Add guest PMU support

On 2015/10/17 1:01, Christopher Covington wrote: > On 10/16/2015 12:55 AM, Wei Huang wrote: >> > >> > >> > On 09/24/2015 05:31 PM, Shannon Zhao wrote: >>> >> This patchset adds guest PMU support for KVM on ARM64. It takes >>> >> trap

Re: [PATCH v3 00/20] KVM: ARM64: Add guest PMU support

On 2015/10/26 19:33, Christoffer Dall wrote: > On Thu, Sep 24, 2015 at 03:31:05PM -0700, Shannon Zhao wrote: >> This patchset adds guest PMU support for KVM on ARM64. It takes >> trap-and-emulate approach. When guest wants to monitor one event, it >> will be trapped by

[PATCH v4 00/21] KVM: ARM64: Add guest PMU support

From: Shannon Zhao This patchset adds guest PMU support for KVM on ARM64. It takes trap-and-emulate approach. When guest wants to monitor one event, it will be trapped by KVM and KVM will call perf_event API to create a perf event and call relevant perf_event APIs to get the count value of event

[PATCH v4 14/21] KVM: ARM64: Add reset and access handlers for PMUSERENR register

From: Shannon Zhao The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown. While the reset value of PMUSERENR is zero, use reset_val_cp15 with zero for its reset handler. Add a helper for CP15 registers reset to specified value. Signed-off-by: Shannon Zhao --- arch/arm64/kvm

[PATCH v4 02/21] KVM: ARM64: Define PMU data structure for each vcpu

From: Shannon Zhao Here we plan to support virtual PMU for guest by full software emulation, so define some basic structs and functions preparing for futher steps. Define struct kvm_pmc for performance monitor counter and struct kvm_pmu for performance monitor unit for each vcpu. According to

[PATCH v4 03/21] KVM: ARM64: Add offset defines for PMU registers

From: Shannon Zhao We are about to trap and emulate acccesses to each PMU register individually. This adds the context offsets for the AArch64 PMU registers and their AArch32 counterparts. Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/kvm_asm.h | 55

[PATCH v4 04/21] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

From: Shannon Zhao Add reset handler which gets host value of PMCR_EL0 and make writable bits architecturally UNKNOWN except PMCR.E to zero. Add a common access handler for PMU registers which emulates writing and reading register and add emulation for PMCR. Signed-off-by: Shannon Zhao

[PATCH v4 01/21] ARM64: Move PMU register related defines to asm/pmu.h

From: Shannon Zhao To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/pmu.h | 45 ++ arch/arm64

[PATCH v4 20/21] KVM: ARM64: Free perf event of PMU when destroying vcpu

From: Shannon Zhao When KVM frees VCPU, it needs to free the perf_event of PMU. Signed-off-by: Shannon Zhao --- arch/arm/kvm/arm.c| 1 + include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c| 21 + 3 files changed, 24 insertions(+) diff --git a/arch/arm/kvm/arm.c b

[PATCH v4 18/21] KVM: ARM64: Add PMU overflow interrupt routing

From: Shannon Zhao When calling perf_event_create_kernel_counter to create perf_event, assign a overflow handler. Then when perf event overflows, set irq_pending and call kvm_vcpu_kick() to sync the interrupt. Signed-off-by: Shannon Zhao --- arch/arm/kvm/arm.c| 4 +++ include/kvm

[PATCH v4 13/21] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register

From: Shannon Zhao Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMOVSSET or PMOVSCLR register. When writing non-zero value to PMOVSSET, pend PMU interrupt. When the value writing to PMOVSCLR is equal to the

[PATCH v4 17/21] KVM: ARM64: Add helper to handle PMCR register bits

From: Shannon Zhao According to ARMv8 spec, when writing 1 to PMCR.E, all counters are enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are disabled. When writing 1 to PMCR.P, reset all event counters, not including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to zero

[PATCH v4 21/21] KVM: ARM64: Add a new kvm ARM PMU device

From: Shannon Zhao Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement the kvm_device_ops for it. Signed-off-by: Shannon Zhao --- Documentation/virtual/kvm/devices/arm-pmu.txt | 15 + arch/arm64/include/uapi/asm/kvm.h | 3 + include/linux/kvm_host.h

[PATCH v4 19/21] KVM: ARM64: Reset PMU state when resetting vcpu

From: Shannon Zhao When resetting vcpu, it needs to reset the PMU state to initial status. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/reset.c | 3 +++ include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c | 19 +++ 3 files changed, 24 insertions(+) diff --git a/arch

[PATCH v4 15/21] KVM: ARM64: Add reset and access handlers for PMSWINC register

From: Shannon Zhao Add access handler which emulates writing and reading PMSWINC register and add support for creating software increment event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 18 +++- include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c| 55

[PATCH v4 11/21] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register

From: Shannon Zhao Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMCNTENSET or PMCNTENCLR register. When writing to PMCNTENSET, call perf_event_enable to enable the perf event. When writing to PMCNTENCLR

[PATCH v4 08/21] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register

From: Shannon Zhao Since the reset value of PMXEVTYPER is UNKNOWN, use reset_unknown or reset_unknown_cp15 for its reset handler. Add access handler which emulates writing and reading PMXEVTYPER register. When writing to PMXEVTYPER, call kvm_pmu_set_counter_event_type to create a perf_event for

[PATCH v4 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

From: Shannon Zhao When we use tools like perf on host, perf passes the event type and the id of this event type category to kernel, then kernel will map them to hardware event number and write this number to PMU PMEVTYPER_EL0 register. When getting the event number in KVM, directly use raw

[PATCH v4 09/21] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register

From: Shannon Zhao Since the reset value of PMXEVCNTR is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMXEVCNTR register. When reading PMXEVCNTR, call perf_event_read_value to get the count value of the perf event. Signed-off-by

[PATCH v4 16/21] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register

From: Shannon Zhao Add access handler which emulates writing and reading PMEVCNTRn and PMEVTYPERn. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 164 ++ 1 file changed, 164 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch

[PATCH v4 06/21] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register

From: Shannon Zhao Add reset handler which gets host value of PMCEID0 or PMCEID1. Since write action to PMCEID0 or PMCEID1 is ignored, add a new case for this. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 29 + 1 file changed, 25 insertions(+), 4

[PATCH v4 12/21] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register

From: Shannon Zhao Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMINTENSET or PMINTENCLR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 34 ++ 1

[PATCH v4 10/21] KVM: ARM64: Add reset and access handlers for PMCCNTR register

From: Shannon Zhao Since the reset value of PMCCNTR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate reading and writing to PMCCNTR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 31 +-- 1 file changed, 29

[PATCH v4 05/21] KVM: ARM64: Add reset and access handlers for PMSELR register

From: Shannon Zhao Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for its reset handler. As it doesn't need to deal with the acsessing action specially, it uses default case to emulate writing and reading PMSELR register. Add a helper for CP15 registers reset to UN

Re: [PATCH v4 18/21] KVM: ARM64: Add PMU overflow interrupt routing

propriate base, > please suggest rules for selecting the more suitable base] > > url: > https://github.com/0day-ci/linux/commits/Shannon-Zhao/KVM-ARM64-Add-guest-PMU-support/20151030-143148 > config: arm-axm55xx_defconfig (attached as .config) > reproduce: > wget

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