Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

On 2015/12/16 4:47, Christoffer Dall wrote: > On Tue, Dec 15, 2015 at 03:59:31PM +, Marc Zyngier wrote: >> > On 15/12/15 15:50, Shannon Zhao wrote: >>> > > >>> > > >>> > > On 2015/12/15 23:33, Marc Zyngier wrote: >>>> &g

Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

Hi, On 2015/12/16 15:31, Shannon Zhao wrote: >>>> >> > But in this case, you're returning an error if it is *not* >>>> >> > initialized. >>>> >> > I understand that in that case you cannot return an interrupt number >>&

Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

On 2015/12/16 17:04, Marc Zyngier wrote: > On 16/12/15 08:06, Shannon Zhao wrote: >> > Hi, >> > >> > On 2015/12/16 15:31, Shannon Zhao wrote: >>>>>>>>> >>>>>>>> But in this case, you're returning an error i

Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

On 2015/12/17 4:33, Christoffer Dall wrote: > On Wed, Dec 16, 2015 at 04:06:49PM +0800, Shannon Zhao wrote: >> Hi, >> >> On 2015/12/16 15:31, Shannon Zhao wrote: >>>>>>>>> But in this case, you're returning an error if it is *not* >>&g

Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

On 2015/12/17 16:33, Marc Zyngier wrote: > On Thu, 17 Dec 2015 15:22:50 +0800 > Shannon Zhao wrote: > >> > >> > >> > On 2015/12/17 4:33, Christoffer Dall wrote: >>> > > On Wed, Dec 16, 2015 at 04:06:49PM +0800, Shannon Zhao wrote: &g

Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

On 2015/12/17 17:38, Marc Zyngier wrote: > On 17/12/15 08:41, Shannon Zhao wrote: >> > >> > >> > On 2015/12/17 16:33, Marc Zyngier wrote: >>> >> On Thu, 17 Dec 2015 15:22:50 +0800 >>> >> Shannon Zhao wrote: >>> >>

[PATCH v8 19/20] KVM: ARM64: Free perf event of PMU when destroying vcpu

From: Shannon Zhao When KVM frees VCPU, it needs to free the perf_event of PMU. Signed-off-by: Shannon Zhao --- arch/arm/kvm/arm.c| 1 + include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c| 21 + 3 files changed, 24 insertions(+) diff --git a/arch/arm/kvm/arm.c b

[PATCH v8 17/20] KVM: ARM64: Add PMU overflow interrupt routing

From: Shannon Zhao When calling perf_event_create_kernel_counter to create perf_event, assign a overflow handler. Then when the perf event overflows, set the corresponding bit of guest PMOVSSET register. If this counter is enabled and its interrupt is enabled as well, kick the vcpu to sync the

[PATCH v8 00/20] KVM: ARM64: Add guest PMU support

From: Shannon Zhao This patchset adds guest PMU support for KVM on ARM64. It takes trap-and-emulate approach. When guest wants to monitor one event, it will be trapped by KVM and KVM will call perf_event API to create a perf event and call relevant perf_event APIs to get the count value of event

[PATCH v8 01/20] ARM64: Move PMU register related defines to asm/pmu.h

From: Shannon Zhao To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/pmu.h | 67 ++ arch/arm64

[PATCH v8 20/20] KVM: ARM64: Add a new kvm ARM PMU device

From: Shannon Zhao Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement the kvm_device_ops for it. Signed-off-by: Shannon Zhao --- Documentation/virtual/kvm/devices/arm-pmu.txt | 24 + arch/arm64/include/uapi/asm/kvm.h | 4 + include/linux/kvm_host.h

[PATCH v8 05/20] KVM: ARM64: Add access handler for PMSELR register

From: Shannon Zhao Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for its reset handler. When reading PMSELR, return the PMSELR.SEL field to guest. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions

[PATCH v8 13/20] KVM: ARM64: Add access handler for PMSWINC register

From: Shannon Zhao Add access handler which emulates writing and reading PMSWINC register and add support for creating software increment event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 18 +- include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c| 33

[PATCH v8 14/20] KVM: ARM64: Add helper to handle PMCR register bits

From: Shannon Zhao According to ARMv8 spec, when writing 1 to PMCR.E, all counters are enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are disabled. When writing 1 to PMCR.P, reset all event counters, not including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to zero

[PATCH v8 02/20] KVM: ARM64: Define PMU data structure for each vcpu

From: Shannon Zhao Here we plan to support virtual PMU for guest by full software emulation, so define some basic structs and functions preparing for futher steps. Define struct kvm_pmc for performance monitor counter and struct kvm_pmu for performance monitor unit for each vcpu. According to

[PATCH v8 18/20] KVM: ARM64: Reset PMU state when resetting vcpu

From: Shannon Zhao When resetting vcpu, it needs to reset the PMU state to initial status. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/reset.c | 3 +++ include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c | 17 + 3 files changed, 22 insertions(+) diff --git a/arch/arm64

[PATCH v8 03/20] KVM: ARM64: Add offset defines for PMU registers

From: Shannon Zhao We are about to trap and emulate accesses to each PMU register individually. This adds the context offsets for the AArch64 PMU registers. Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/kvm_host.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a

[PATCH v8 11/20] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register

From: Shannon Zhao Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a handler to emulate writing PMINTENSET or PMINTENCLR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 27 +++ 1 file

[PATCH v8 06/20] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register

From: Shannon Zhao Add access handler which gets host value of PMCEID0 or PMCEID1 when guest access these registers. Writing action to PMCEID0 or PMCEID1 is UNDEFINED. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 27 +++ 1 file changed, 23 insertions

[PATCH v8 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

From: Shannon Zhao When we use tools like perf on host, perf passes the event type and the id of this event type category to kernel, then kernel will map them to hardware event number and write this number to PMU PMEVTYPER_EL0 register. When getting the event number in KVM, directly use raw

[PATCH v8 10/20] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register

From: Shannon Zhao Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a handler to emulate writing PMCNTENSET or PMCNTENCLR register. When writing to PMCNTENSET, call perf_event_enable to enable the perf event. When writing to PMCNTENCLR

[PATCH v8 04/20] KVM: ARM64: Add access handler for PMCR register

From: Shannon Zhao Add reset handler which gets host value of PMCR_EL0 and make writable bits architecturally UNKNOWN except PMCR.E which is zero. Add an access handler for PMCR. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 39 +-- 1 file

[PATCH v8 15/20] KVM: ARM64: Add a helper to forward trap to guest EL1

From: Shannon Zhao This helper forward the trap caused by MRS/MSR for arch64 and MCR/MRC, MCRR/MRRC for arch32 CP15 to guest EL1. Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/kvm_emulate.h | 1 + arch/arm64/kvm/inject_fault.c| 52 +++- 2

[PATCH v8 16/20] KVM: ARM64: Add access handler for PMUSERENR register

From: Shannon Zhao This register resets as unknown in 64bit mode while it resets as zero in 32bit mode. Here we choose to reset it as zero for consistency. PMUSERENR_EL0 holds some bits which decide whether PMU registers can be accessed from EL0. Add some check helpers to handle the access from

[PATCH v8 08/20] KVM: ARM64: Add access handler for event typer register

From: Shannon Zhao These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER which is mapped to PMEVTYPERn or PMCCFILTR. The access handler translates all aarch32 register offsets to aarch64 ones and uses vcpu_sys_reg() to access their values to avoid taking care of big endian. When

[PATCH v8 12/20] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register

From: Shannon Zhao Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use reset_unknown for its reset handler. Add a handler to emulate writing PMOVSSET or PMOVSCLR register. When writing non-zero value to PMOVSSET, the counter and its interrupt is enabled, kick this vcpu to sync PMU

[PATCH v8 09/20] KVM: ARM64: Add access handler for event counter register

From: Shannon Zhao These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which is mapped to PMEVCNTRn. The access handler translates all aarch32 register offsets to aarch64 ones and uses vcpu_sys_reg() to access their values to avoid taking care of big endian. When reading these

Re: [PATCH 2/2] arm64: KVM: Do not update PC if the trap handler has updated it

ading to a mildly confused > guest. > > Solve this by snapshoting PC before the access is performed, > and checking if it has moved or not before incrementing it. > Thanks a lot. This solves the problem of guest PMU failing to inject EL1 fault to guest. Tested-by: Shannon Zhao Reviewed-

Re: [PATCH 1/2] arm: KVM: Do not update PC if the trap handler has updated it

ading to a mildly confused > guest. > > Solve this by snapshoting PC before the access is performed, > and checking if it has moved or not before incrementing it. > > Reported-by: Shannon Zhao > Signed-off-by: Marc Zyngier Reviewed-by: Shannon Zhao > --- > arch/ar

Re: [PATCH v8 08/20] KVM: ARM64: Add access handler for event typer register

On 2016/1/7 19:03, Marc Zyngier wrote: > On 22/12/15 08:08, Shannon Zhao wrote: >> > From: Shannon Zhao >> > >> > These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER >> > which is mapped to PMEVTYPERn or PMCCFILTR. >> > >>

Re: [PATCH v8 16/20] KVM: ARM64: Add access handler for PMUSERENR register

On 2016/1/7 18:14, Marc Zyngier wrote: > On 22/12/15 08:08, Shannon Zhao wrote: >> > From: Shannon Zhao >> > >> > This register resets as unknown in 64bit mode while it resets as zero >> > in 32bit mode. Here we choose to reset it as zero for consisten

Re: [PATCH v8 04/20] KVM: ARM64: Add access handler for PMCR register

On 2016/1/7 18:43, Marc Zyngier wrote: > On 22/12/15 08:07, Shannon Zhao wrote: >> > From: Shannon Zhao >> > >> > Add reset handler which gets host value of PMCR_EL0 and make writable >> > bits architecturally UNKNOWN except PMCR.E which is ze

Re: [PATCH v8 08/20] KVM: ARM64: Add access handler for event typer register

On 2015/12/22 16:08, Shannon Zhao wrote: > From: Shannon Zhao > > These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER > which is mapped to PMEVTYPERn or PMCCFILTR. > > The access handler translates all aarch32 register offsets to aarch64 > ones and u

Re: [PATCH v8 08/20] KVM: ARM64: Add access handler for event typer register

On 2016/1/7 19:03, Marc Zyngier wrote: > On 22/12/15 08:08, Shannon Zhao wrote: >> > From: Shannon Zhao >> > >> > These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER >> > which is mapped to PMEVTYPERn or PMCCFILTR. >> > >>

[PATCH 00/18] KVM: ARM64: Add guest PMU support

From: Shannon Zhao This patchset adds guest PMU support for KVM on ARM64. It takes trap-and-emulate approach. When guest wants to monitor one event, it will be trapped by KVM and KVM will call perf_event API to create a perf event and call relevant perf_event APIs to get the count value of event

[PATCH 03/18] KVM: ARM64: Add offset defines for PMU registers

From: Shannon Zhao We are about to trap and emulate acccesses to each PMU register individually. This adds the context offsets for the AArch64 PMU registers and their AArch32 counterparts. Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/kvm_asm.h | 59

[PATCH 02/18] KVM: ARM64: Add initial support for PMU

From: Shannon Zhao Here we plan to support virtual PMU for guest by full software emulation, so define some basic structs and functions preparing for futher steps. Define struct kvm_pmc for performance monitor counter and struct kvm_pmu for performance monitor unit for each vcpu. According to

[PATCH 01/18] ARM64: Move PMU register related defines to asm/pmu.h

From: Shannon Zhao To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/pmu.h | 45 ++ arch/arm64

[PATCH 05/18] KVM: ARM64: Add reset and access handlers for PMSELR_EL0 register

From: Shannon Zhao Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMSELR_EL0 register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 26 +- 1 file changed, 25

[PATCH 15/18] KVM: ARM64: Add reset and access handlers for PMSWINC_EL0 register

From: Shannon Zhao Add access handler which emulates writing and reading PMSWINC_EL0 register and add support for creating software increment event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 15 ++- include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c

[PATCH 13/18] KVM: ARM64: Add reset and access handlers for PMOVSSET_EL0 and PMOVSCLR_EL0 register

From: Shannon Zhao Since the reset value of PMOVSSET_EL0 and PMOVSCLR_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMOVSSET_EL0 or PMOVSCLR_EL0 register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 30

[PATCH 14/18] KVM: ARM64: Add reset and access handlers for PMUSERENR_EL0 register

From: Shannon Zhao Since the reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMUSERENR_EL0 register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 15 ++- include/kvm/arm_pmu.h

[PATCH 10/18] KVM: ARM64: Add reset and access handlers for PMCCNTR_EL0 register

From: Shannon Zhao Since the reset value of PMCCNTR_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMCCNTR_EL0 register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 19 ++- 1 file changed, 18

[PATCH 08/18] KVM: ARM64: Add reset and access handlers for PMXEVTYPER_EL0 register

From: Shannon Zhao Since the reset value of PMXEVTYPER_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMXEVTYPER_EL0 register. When writing to PMXEVTYPER_EL0, call kvm_pmu_set_counter_event_type create a perf event for the selected

[PATCH 18/18] KVM: ARM64: Add KVM_CAP_ARM_PMU and KVM_ARM_PMU_SET_IRQ

From: Shannon Zhao Add KVM_CAP_ARM_PMU for userspace to check whether KVM supports PMU. Add KVM_ARM_PMU_SET_IRQ for userspace to set PMU IRQ number. Signed-off-by: Shannon Zhao --- arch/arm/kvm/arm.c | 8 include/kvm/arm_pmu.h| 5 + include/uapi/linux/kvm.h | 4

[PATCH 16/18] KVM: ARM64: Add access handlers for PMEVCNTRn_EL0 and PMEVTYPERn_EL0 register

From: Shannon Zhao Add access handler which emulates writing and reading PMEVCNTRn_EL0 and PMEVTYPERn_EL0. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 106 ++ 1 file changed, 106 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c

[PATCH 09/18] KVM: ARM64: Add reset and access handlers for PMXEVCNTR_EL0 register

From: Shannon Zhao Since the reset value of PMXEVTYPER_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMXEVTYPER_EL0 register. When reading PMXEVCNTR_EL0, call perf_event_read_value to get the count value of the perf event. Signed

[PATCH 06/18] KVM: ARM64: Add reset and access handlers for PMCEID0_EL0 and PMCEID1_EL0 register

From: Shannon Zhao Add reset handler which gets host value of PMCEID0_EL0 or PMCEID1_EL0. Add access handler which emulates writing and reading PMCEID0_EL0 or PMCEID1_EL0 register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 36 ++-- 1 file

[PATCH 04/18] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

From: Shannon Zhao Add reset handler which gets host value of PMCR_EL0 and make writable bits architecturally UNKNOWN. Add access handler which emulates writing and reading PMCR_EL0 register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 41

[PATCH 17/18] KVM: ARM64: Add PMU overflow interrupt routing

From: Shannon Zhao When calling perf_event_create_kernel_counter to create perf_event, assign a overflow handler. Then when perf event overflows, if vcpu doesn't run, call irq_work_queue to wake up vcpu. Otherwise call kvm_vgic_inject_irq to inject the interrupt. Signed-off-by: Shannon

[PATCH 12/18] KVM: ARM64: Add reset and access handlers for PMINTENSET_EL1 and PMINTENCLR_EL1 register

From: Shannon Zhao Since the reset value of PMINTENSET_EL1 and PMINTENCLR_EL1 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMINTENSET_EL1 or PMINTENCLR_EL1 register. When writing to PMINTENSET_EL1, set the interrupt flag true. While

[PATCH 07/18] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

From: Shannon Zhao When we use tools like perf on host, perf passes the event type and the id in this type category to kernel, then kernel will map them to event number and write this number to PMU PMEVTYPER_EL0 register. While we're trapping and emulating guest accesses to PMU registers, w

[PATCH 11/18] KVM: ARM64: Add reset and access handlers for PMCNTENSET_EL0 and PMCNTENCLR_EL0 register

From: Shannon Zhao Since the reset value of PMCNTENSET_EL0 and PMCNTENCLR_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMCNTENSET_EL0 or PMCNTENCLR_EL0 register. When writing to PMCNTENSET_EL0, call perf_event_enable to enable the

Re: [PATCH 02/18] KVM: ARM64: Add initial support for PMU

On 2015/7/17 2:25, Christoffer Dall wrote: > On Mon, Jul 06, 2015 at 10:17:32AM +0800, shannon.z...@linaro.org wrote: >> From: Shannon Zhao >> >> Here we plan to support virtual PMU for guest by full software >> emulation, so define some basic structs and functions pr

Re: [PATCH 03/18] KVM: ARM64: Add offset defines for PMU registers

On 2015/7/17 2:45, Christoffer Dall wrote: > On Mon, Jul 06, 2015 at 10:17:33AM +0800, shannon.z...@linaro.org wrote: >> From: Shannon Zhao >> >> We are about to trap and emulate acccesses to each PMU register >> individually. This adds the context offsets for the A

Re: [PATCH 04/18] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

On 2015/7/17 3:55, Christoffer Dall wrote: > On Mon, Jul 06, 2015 at 10:17:34AM +0800, shannon.z...@linaro.org wrote: >> From: Shannon Zhao >> >> Add reset handler which gets host value of PMCR_EL0 and make writable >> bits architecturally UNKNOWN. Add access handle

Re: [PATCH 02/18] KVM: ARM64: Add initial support for PMU

On 2015/7/17 17:58, Christoffer Dall wrote: On Fri, Jul 17, 2015 at 04:13:35PM +0800, Shannon Zhao wrote: On 2015/7/17 2:25, Christoffer Dall wrote: On Mon, Jul 06, 2015 at 10:17:32AM +0800, shannon.z...@linaro.org wrote: From: Shannon Zhao Here we plan to support virtual PMU for guest

Re: [PATCH 03/18] KVM: ARM64: Add offset defines for PMU registers

On 2015/7/17 18:17, Christoffer Dall wrote: On Fri, Jul 17, 2015 at 04:25:06PM +0800, Shannon Zhao wrote: On 2015/7/17 2:45, Christoffer Dall wrote: On Mon, Jul 06, 2015 at 10:17:33AM +0800, shannon.z...@linaro.org wrote: From: Shannon Zhao We are about to trap and emulate acccesses to

Re: [PATCH 04/18] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

On 2015/7/17 18:21, Christoffer Dall wrote: > On Fri, Jul 17, 2015 at 04:45:44PM +0800, Shannon Zhao wrote: >> >> >> On 2015/7/17 3:55, Christoffer Dall wrote: >>> On Mon, Jul 06, 2015 at 10:17:34AM +0800, shannon.z...@linaro.org wrote: >>>> From: Shann

Re: [PATCH 07/18] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

On 2015/7/17 22:30, Christoffer Dall wrote: > On Mon, Jul 06, 2015 at 10:17:37AM +0800, shannon.z...@linaro.org wrote: >> From: Shannon Zhao >> >> When we use tools like perf on host, perf passes the event type and the >> id in this type category to kernel, then ke

[PATCH v2 13/22] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register

From: Shannon Zhao Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMINTENSET or PMINTENCLR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 34 ++ 1

[PATCH v2 01/22] ARM64: Move PMU register related defines to asm/pmu.h

From: Shannon Zhao To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/pmu.h | 45 ++ arch/arm64

[PATCH v2 17/22] KVM: ARM64: Add reset and access handlers for PMSWINC register

From: Shannon Zhao Add access handler which emulates writing and reading PMSWINC register and add support for creating software increment event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 18 +- include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c| 33

[PATCH v2 19/22] KVM: ARM64: Add PMU overflow interrupt routing

From: Shannon Zhao When calling perf_event_create_kernel_counter to create perf_event, assign a overflow handler. Then when perf event overflows, set irq_pending and call kvm_vcpu_kick() to sync the interrupt. Signed-off-by: Shannon Zhao --- arch/arm/kvm/arm.c| 3 +++ include/kvm

[PATCH v2 18/22] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register

From: Shannon Zhao Add access handler which emulates writing and reading PMEVCNTRn and PMEVTYPERn. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 164 ++ 1 file changed, 164 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch

[PATCH v2 09/22] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register

From: Shannon Zhao Since the reset value of PMXEVTYPER is UNKNOWN, use reset_unknown or reset_unknown_cp15 for its reset handler. Add access handler which emulates writing and reading PMXEVTYPER register. When writing to PMXEVTYPER, call kvm_pmu_set_counter_event_type to create a perf_event for

[PATCH v2 22/22] KVM: ARM64: Add a new kvm ARM PMU device

From: Shannon Zhao Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement the kvm_device_ops for it. Signed-off-by: Shannon Zhao --- Documentation/virtual/kvm/devices/arm-pmu.txt | 15 + arch/arm64/include/uapi/asm/kvm.h | 3 + include/linux/kvm_host.h

[PATCH v2 02/22] KVM: ARM64: Define PMU data structure for each vcpu

From: Shannon Zhao Here we plan to support virtual PMU for guest by full software emulation, so define some basic structs and functions preparing for futher steps. Define struct kvm_pmc for performance monitor counter and struct kvm_pmu for performance monitor unit for each vcpu. According to

[PATCH v2 07/22] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register

From: Shannon Zhao Add reset handler which gets host value of PMCEID0 or PMCEID1. Since write action to PMCEID0 or PMCEID1 is ignored, add a new case for this. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 36 1 file changed, 32 insertions

[PATCH v2 15/22] KVM: ARM64: Add a helper for CP15 registers reset to specified value

From: Shannon Zhao Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.h | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h index a0b3811..a476b1b 100644 --- a/arch/arm64/kvm/sys_regs.h +++ b/arch/arm64/kvm/sys_regs.h @@ -119,6

[PATCH v2 03/22] KVM: ARM64: Add offset defines for PMU registers

From: Shannon Zhao We are about to trap and emulate acccesses to each PMU register individually. This adds the context offsets for the AArch64 PMU registers and their AArch32 counterparts. Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/kvm_asm.h | 59

[PATCH v2 04/22] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

From: Shannon Zhao Add reset handler which gets host value of PMCR_EL0 and make writable bits architecturally UNKNOWN. Add a common access handler for PMU registers which emulates writing and reading register and add emulation for PMCR. Signed-off-by: Shannon Zhao --- arch/arm64/kvm

[PATCH v2 20/22] KVM: ARM64: Reset PMU state when resetting vcpu

From: Shannon Zhao Signed-off-by: Shannon Zhao --- arch/arm64/kvm/reset.c | 3 +++ include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c | 18 ++ 3 files changed, 23 insertions(+) diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 0b43265..ee2c2e9 100644

[PATCH v2 14/22] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register

From: Shannon Zhao Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMOVSSET or PMOVSCLR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 33 ++--- 1 file

[PATCH v2 06/22] KVM: ARM64: Add reset and access handlers for PMSELR register

From: Shannon Zhao Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for its reset handler. As it doesn't need to deal with the acsessing action specially, it uses default case to emulate writing and reading PMSELR register. Signed-off-by: Shannon Zhao --- arch/arm6

[PATCH v2 21/22] KVM: ARM64: Free perf event of PMU when destroying vcpu

From: Shannon Zhao When KVM frees VCPU, it needs to free the perf_event of PMU. Signed-off-by: Shannon Zhao --- arch/arm/kvm/arm.c| 1 + include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c| 21 + 3 files changed, 24 insertions(+) diff --git a/arch/arm/kvm/arm.c b

[PATCH v2 00/22] KVM: ARM64: Add guest PMU support

From: Shannon Zhao This patchset adds guest PMU support for KVM on ARM64. It takes trap-and-emulate approach. When guest wants to monitor one event, it will be trapped by KVM and KVM will call perf_event API to create a perf event and call relevant perf_event APIs to get the count value of event

[PATCH v2 11/22] KVM: ARM64: Add reset and access handlers for PMCCNTR register

From: Shannon Zhao Since the reset value of PMCCNTR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate reading to PMCCNTR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 17 +++-- 1 file changed, 15 insertions(+), 2 deletions

[PATCH v2 16/22] KVM: ARM64: Add reset and access handlers for PMUSERENR register

From: Shannon Zhao Since the reset value of PMUSERENR is zero, use reset_val(_cp15) with zero for its reset handler. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm

[PATCH v2 10/22] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register

From: Shannon Zhao Since the reset value of PMXEVCNTR is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMXEVCNTR register. When reading PMXEVCNTR, call perf_event_read_value to get the count value of the perf event. Signed-off-by

[PATCH v2 08/22] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

From: Shannon Zhao When we use tools like perf on host, perf passes the event type and the id of this event type category to kernel, then kernel will map them to hardware event number and write this number to PMU PMEVTYPER_EL0 register. While we're trapping and emulating guest accesses t

[PATCH v2 12/22] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register

From: Shannon Zhao Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMCNTENSET or PMCNTENCLR register. When writing to PMCNTENSET, call perf_event_enable to enable the perf event. When writing to PMCNTENCLR

[PATCH v2 05/22] KVM: ARM64: Add a helper for CP15 registers reset to UNKNOWN

From: Shannon Zhao Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.h | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h index d411e25..a0b3811 100644 --- a/arch/arm64/kvm/sys_regs.h +++ b/arch/arm64/kvm/sys_regs.h @@ -104,6

Re: [PATCH v2 02/22] KVM: ARM64: Define PMU data structure for each vcpu

On 2015/9/11 17:10, Marc Zyngier wrote: > On 11/09/15 09:54, Shannon Zhao wrote: >> From: Shannon Zhao >> >> Here we plan to support virtual PMU for guest by full software >> emulation, so define some basic structs and functions preparing for >> futher

Re: [PATCH v2 08/22] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

On 2015/9/11 19:04, Marc Zyngier wrote: On 11/09/15 09:55, Shannon Zhao wrote: From: Shannon Zhao When we use tools like perf on host, perf passes the event type and the id of this event type category to kernel, then kernel will map them to hardware event number and write this number to PMU

Re: [PATCH v2 04/22] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

On 2015/9/11 18:07, Marc Zyngier wrote: > On 11/09/15 09:54, Shannon Zhao wrote: >> > From: Shannon Zhao >> > >> > Add reset handler which gets host value of PMCR_EL0 and make writable >> > bits architecturally UNKNOWN. Add a common access handler for PM

Re: [PATCH v2 00/22] KVM: ARM64: Add guest PMU support

On 2015/9/14 19:53, Christoffer Dall wrote: Hi Shannon, On Fri, Sep 11, 2015 at 04:54:53PM +0800, Shannon Zhao wrote: From: Shannon Zhao This patchset adds guest PMU support for KVM on ARM64. It takes trap-and-emulate approach. When guest wants to monitor one event, it will be trapped by

Re: [PATCH v2 00/22] KVM: ARM64: Add guest PMU support

in struct kvm_pmc * Fix the handle of cp15 regs * Create a new kvm device vPMU, then userspace could choose whether to create PMU * Fix the handle of PMU overflow interrupt On 2015/9/11 16:54, Shannon Zhao wrote: From: Shannon Zhao This patchset adds guest PMU support for KVM on ARM64. It takes t

Re: [PATCH v2 00/22] KVM: ARM64: Add guest PMU support

Hi Wei, On 2015/9/17 5:07, Wei Huang wrote: > I am testing this series. Thanks for your time and help. > The first question is: do you plan to add ACPI > support in QEMU? To the completeness, this should be added. Maybe this could be added at v3. But I have a look at the kernel PMU driver, it do

Re: [PATCH v2 00/22] KVM: ARM64: Add guest PMU support

Hi Wei, On 2015/9/17 13:56, Wei Huang wrote: > > > On 09/16/2015 08:32 PM, Shannon Zhao wrote: >> Hi Wei, >> >> On 2015/9/17 5:07, Wei Huang wrote: >>> I am testing this series. >> Thanks for your time and help. >> >>> The first questio

Re: [PATCH v2 00/22] KVM: ARM64: Add guest PMU support

Hi Andrew, On 2015/9/17 17:30, Andrew Jones wrote: > On Thu, Sep 17, 2015 at 09:32:34AM +0800, Shannon Zhao wrote: >> > Hi Wei, >> > >> > On 2015/9/17 5:07, Wei Huang wrote: >>> > > I am testing this series. >> > Thanks for your time and hel

[PATCH v3 02/20] KVM: ARM64: Define PMU data structure for each vcpu

contains at most 32(ARMV8_MAX_COUNTERS) counters. Since this only supports ARM64 (or PMUv3), add a separate config symbol for it. Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/kvm/Kconfig| 8 include/kvm/arm_pmu.h | 40

[PATCH v3 00/20] KVM: ARM64: Add guest PMU support

handler instead of adding alone handler for each register * Try to use the sys_regs to store the register value instead of adding new variables in struct kvm_pmc * Fix the handle of cp15 regs * Create a new kvm device vPMU, then userspace could choose whether to create PMU * Fix the handle of P

[PATCH v3 01/20] ARM64: Move PMU register related defines to asm/pmu.h

To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/pmu.h | 45 ++ arch/arm64/kernel/perf_event.c

[PATCH v3 09/20] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register

Since the reset value of PMXEVCNTR is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMXEVCNTR register. When reading PMXEVCNTR, call perf_event_read_value to get the count value of the perf event. Signed-off-by: Shannon Zhao --- arch

[PATCH v3 08/20] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register

type. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 19 +-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d49657a..605972e 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm

[PATCH v3 04/20] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

Add reset handler which gets host value of PMCR_EL0 and make writable bits architecturally UNKNOWN. Add a common access handler for PMU registers which emulates writing and reading register and add emulation for PMCR. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 81

[PATCH v3 03/20] KVM: ARM64: Add offset defines for PMU registers

We are about to trap and emulate acccesses to each PMU register individually. This adds the context offsets for the AArch64 PMU registers and their AArch32 counterparts. Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/kvm_asm.h | 59 +++- 1 file

[PATCH v3 05/20] KVM: ARM64: Add reset and access handlers for PMSELR register

Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for its reset handler. As it doesn't need to deal with the acsessing action specially, it uses default case to emulate writing and reading PMSELR register. Add a helper for CP15 registers reset to UNKNOWN. Signed-off-by: Sh

[PATCH v3 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

perf_event for it. Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/pmu.h | 2 + arch/arm64/kvm/Makefile | 1 + include/kvm/arm_pmu.h| 13 virt/kvm/arm/pmu.c | 154 +++ 4 files changed, 170 insertions(+) create mode

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