Hi all,
I have a problem that I want to ask for your advice.
Before I send this mail to Marc and Christoffer. But it seems that they are
busy or not online recently.
I git clone Marc's "kvmtool-vgic-dyn" branch and run it on Fastmodel
Cortex-A57*4 with qemu 2.1.0.
https://git.kernel.org/pub/scm
On 2014/9/25 21:35, Christoffer Dall wrote:
> On Thu, Sep 25, 2014 at 08:44:16PM +0800, Shannon Zhao wrote:
>> Hi all,
>>
>> I have a problem that I want to ask for your advice.
>> Before I send this mail to Marc and Christoffer. But it seems that they are
>
the expected purpose.
>
> This showed up as bugs in kfree() and the kernel complaining a lot of
> you turn on memory debugging.
>
> This addresses: http://marc.info/?l=kvm&m=141164910007868&w=2
>
> Reported-by: Shannon Zhao
> Signed-off-by: Christoffer Dall
>
On 2014/9/26 16:44, Christoffer Dall wrote:
> Hi Shannon,
>
> On Fri, Sep 26, 2014 at 01:57:46PM +0800, Shannon Zhao wrote:
>>
>> On 2014/9/26 1:49, Christoffer Dall wrote:
>>> The sgi values calculated in read_set_clear_sgi_pend_reg() and
>>> write
the expected purpose.
>
> This showed up as bugs in kfree() and the kernel complaining a lot of
> you turn on memory debugging.
>
> This addresses: http://marc.info/?l=kvm&m=141164910007868&w=2
>
> Reported-by: Shannon Zhao
> Signed-off-by: Christoffer Dall
>
Hi Christoffer,
On 2014/9/26 21:44, Christoffer Dall wrote:
> On Fri, Sep 26, 2014 at 12:16:35PM +0200, Christoffer Dall wrote:
>> On Fri, Sep 26, 2014 at 05:26:00PM +0800, Shannon Zhao wrote:
>>>
>>>
>>> On 2014/9/26 16:44, Christoffer Dall wrote:
>>>
Hi Nikolay,
>From this mail I know you guys have done some work about ioeventfd support
on kvm-arm before. Do you have plan to rework your patch based on
the new branch? If not, I think we should send a patch to make eventfd
support on kvm-arm and make vhost-net work.
Based on the new kvm-arm bran
On 2014/11/25 5:26, Nikolay Nikolaev wrote:
> In io_mem_abort remove the call to vgic_handle_mmio. The target is to have
> a single MMIO handling path - that is through the kvm_io_bus_ API.
>
> Register a kvm_io_device in kvm_vgic_init on the whole vGIC MMIO region.
> Both read and write calls are
On 2014/11/25 5:27, Nikolay Nikolaev wrote:
> This enables compilation of the eventfd feature on ARM.
>
Only enable on ARM? I think we should enable it on ARM64 as well because the
eventfd featrue is common for ARM32 and ARM64.
Thanks,
Shannon
> Signed-off-by: Nikolay Nikolaev
> ---
> arch/a
On 2015/11/3 4:13, Christopher Covington wrote:
> On 10/30/2015 02:21 AM, Shannon Zhao wrote:
>> From: Shannon Zhao
>>
>> When we use tools like perf on host, perf passes the event type and the
>> id of this event type category to kernel, then kernel will map them
On 2015/11/3 4:54, Christopher Covington wrote:
> Hi Shannon,
>
> On 10/30/2015 02:21 AM, Shannon Zhao wrote:
>> From: Shannon Zhao
>>
>> Since the reset value of PMXEVTYPER is UNKNOWN, use reset_unknown or
>> reset_unknown_cp15 for its reset handler. Add
On 2015/11/2 17:13, Xiao Guangrong wrote:
> Implement CreateField term which is used by NVDIMM _DSM method in later patch
>
> Signed-off-by: Xiao Guangrong
> ---
> hw/acpi/aml-build.c | 13 +
> include/hw/acpi/aml-build.h | 1 +
> 2 files changed, 14 insertions(+)
>
> dif
Hi Marc,
On 2015/11/30 19:42, Marc Zyngier wrote:
>> +static void reset_pmceid(struct kvm_vcpu *vcpu, const struct sys_reg_desc
>> *r)
>> > +{
>> > + u64 pmceid;
>> > +
>> > + if (r->reg == PMCEID0_EL0 || r->reg == c9_PMCEID0)
> That feels wrong. We should only reset the 64bit view of the sysre
Hi Marc,
On 2015/12/1 1:56, Marc Zyngier wrote:
> Same remark here as the one I made earlier. I'm pretty sure we don't
> call any CP15 reset because they are all shared with their 64bit
> counterparts. The same thing goes for the whole series.
Ok, I see. But within the 64bit reset function, it nee
Hi Marc,
On 2015/12/1 2:34, Marc Zyngier wrote:
> On Fri, 30 Oct 2015 14:21:42 +0800
> Shannon Zhao wrote:
>
> Hi Shannon,
>
>> > From: Shannon Zhao
>> >
>> > This patchset adds guest PMU support for KVM on ARM64. It takes
>> > trap-and-emul
On 2015/12/1 2:12, Marc Zyngier wrote:
> On Fri, 30 Oct 2015 14:21:50 +0800
> Shannon Zhao wrote:
>
>> > From: Shannon Zhao
>> >
>> > Since the reset value of PMXEVTYPER is UNKNOWN, use reset_unknown or
>> > reset_unknown_cp15 for its reset ha
On 2015/12/1 16:49, Marc Zyngier wrote:
> On 01/12/15 01:51, Shannon Zhao wrote:
>> Hi Marc,
>>
>> On 2015/12/1 1:56, Marc Zyngier wrote:
>>> Same remark here as the one I made earlier. I'm pretty sure we don't
>>> call any CP15 reset because they
On 2015/12/1 2:22, Marc Zyngier wrote:
> On Fri, 30 Oct 2015 14:22:00 +0800
> Shannon Zhao wrote:
>
>> From: Shannon Zhao
>>
>> When calling perf_event_create_kernel_counter to create perf_event,
>> assign a overflow handler. Then when perf event overf
On 2015/12/1 22:50, Marc Zyngier wrote:
On 01/12/15 14:35, Shannon Zhao wrote:
On 2015/12/1 2:22, Marc Zyngier wrote:
On Fri, 30 Oct 2015 14:22:00 +0800
Shannon Zhao wrote:
From: Shannon Zhao
When calling perf_event_create_kernel_counter to create perf_event,
assign a overflow handler
On 2015/12/1 23:41, Marc Zyngier wrote:
The reason is that when guest clear the overflow register, it will trap
>to kvm and call kvm_pmu_sync_hwstate() as you see above. At this moment,
>the overflow register is still overflowed(that is some bit is still 1).
>So We need to use some flag to mark
On 2015/12/2 0:57, Marc Zyngier wrote:
> On 01/12/15 16:26, Shannon Zhao wrote:
>>
>>
>> On 2015/12/1 23:41, Marc Zyngier wrote:
>>>> The reason is that when guest clear the overflow register, it will trap
>>>>> to kvm and call kvm_pmu_sync_hwsta
On 2015/12/2 16:45, Marc Zyngier wrote:
> On 02/12/15 02:40, Shannon Zhao wrote:
>> >
>> >
>> > On 2015/12/2 0:57, Marc Zyngier wrote:
>>> >> On 01/12/15 16:26, Shannon Zhao wrote:
>>>> >>>
>>>> >>>
>
From: Shannon Zhao
Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. As it doesn't need to deal with the accessing action
specially, it uses default case to emulate writing and reading PMSELR
register.
Signed-off-by: Shannon Zhao
---
arch/arm6
From: Shannon Zhao
This patchset adds guest PMU support for KVM on ARM64. It takes
trap-and-emulate approach. When guest wants to monitor one event, it
will be trapped by KVM and KVM will call perf_event API to create a perf
event and call relevant perf_event APIs to get the count value of event
From: Shannon Zhao
When resetting vcpu, it needs to reset the PMU state to initial status.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/reset.c | 3 +++
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c | 18 ++
3 files changed, 23 insertions(+)
diff --git a/arch
From: Shannon Zhao
We are about to trap and emulate acccesses to each PMU register
individually. This adds the context offsets for the AArch64 PMU
registers and their AArch32 counterparts.
Signed-off-by: Shannon Zhao
---
arch/arm64/include/asm/kvm_asm.h | 55
From: Shannon Zhao
Since the reset value of PMXEVCNTR is UNKNOWN, use reset_unknown for
its reset handler. Add access handler which emulates writing and reading
PMXEVCNTR register. When reading PMXEVCNTR, call perf_event_read_value
to get the count value of the perf event.
Signed-off-by
From: Shannon Zhao
Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMCNTENSET or PMCNTENCLR register.
When writing to PMCNTENSET, call perf_event_enable to enable the perf
event. When writing to PMCNTENCLR
From: Shannon Zhao
Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMINTENSET or PMINTENCLR register.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 34 ++
1
From: Shannon Zhao
Add reset handler which gets host value of PMCR_EL0 and make writable
bits architecturally UNKNOWN except PMCR.E to zero. Add a common access
handler for PMU registers which emulates writing and reading register
and add emulation for PMCR.
Signed-off-by: Shannon Zhao
From: Shannon Zhao
To use the ARMv8 PMU related register defines from the KVM code,
we move the relevant definitions to asm/pmu.h header file.
Signed-off-by: Anup Patel
Signed-off-by: Shannon Zhao
---
arch/arm64/include/asm/pmu.h | 64 ++
arch/arm64
From: Shannon Zhao
Since the reset value of PMXEVTYPER is UNKNOWN, use reset_unknown or
reset_unknown_cp15 for its reset handler. Add access handler which
emulates writing and reading PMXEVTYPER register. When writing to
PMXEVTYPER, call kvm_pmu_set_counter_event_type to create a perf_event
for
From: Shannon Zhao
Since the reset value of PMCCNTR is UNKNOWN, use reset_unknown for its
reset handler. Add a new case to emulate reading and writing to PMCCNTR
register.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 31 +--
1 file changed, 29
From: Shannon Zhao
Add reset handler which gets host value of PMCEID0 or PMCEID1. Since
write action to PMCEID0 or PMCEID1 is ignored, add a new case for this.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 29 +
1 file changed, 25 insertions(+), 4
From: Shannon Zhao
When we use tools like perf on host, perf passes the event type and the
id of this event type category to kernel, then kernel will map them to
hardware event number and write this number to PMU PMEVTYPER_EL0
register. When getting the event number in KVM, directly use raw
From: Shannon Zhao
When KVM frees VCPU, it needs to free the perf_event of PMU.
Signed-off-by: Shannon Zhao
---
arch/arm/kvm/arm.c| 1 +
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 21 +
3 files changed, 24 insertions(+)
diff --git a/arch/arm/kvm/arm.c b
From: Shannon Zhao
Add access handler which emulates writing and reading PMSWINC
register and add support for creating software increment event.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 18 +-
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 44
From: Shannon Zhao
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
disabled. When writing 1 to PMCR.P, reset all event counters, not
including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to
zero
From: Shannon Zhao
Here we plan to support virtual PMU for guest by full software
emulation, so define some basic structs and functions preparing for
futher steps. Define struct kvm_pmc for performance monitor counter and
struct kvm_pmu for performance monitor unit for each vcpu. According to
From: Shannon Zhao
Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
the kvm_device_ops for it.
Signed-off-by: Shannon Zhao
---
Documentation/virtual/kvm/devices/arm-pmu.txt | 16 +
arch/arm64/include/uapi/asm/kvm.h | 3 +
include/linux/kvm_host.h
From: Shannon Zhao
Add access handler which emulates writing and reading PMEVCNTRn and
PMEVTYPERn.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 164 ++
1 file changed, 164 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch
From: Shannon Zhao
The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f5e0732..eb4fcf9
From: Shannon Zhao
Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMOVSSET or PMOVSCLR register.
When writing non-zero value to PMOVSSET, pend PMU interrupt. When the
value writing to PMOVSCLR is equal to the
From: Shannon Zhao
When calling perf_event_create_kernel_counter to create perf_event,
assign a overflow handler. Then when perf event overflows, call
kvm_vcpu_kick() to sync the interrupt.
Signed-off-by: Shannon Zhao
---
arch/arm/kvm/arm.c| 2 ++
include/kvm/arm_pmu.h | 2 ++
virt/kvm
On 2015/12/7 22:06, Marc Zyngier wrote:
On 03/12/15 06:11, Shannon Zhao wrote:
From: Shannon Zhao
We are about to trap and emulate acccesses to each PMU register
s/acccesses/accesses/
individually. This adds the context offsets for the AArch64 PMU
registers and their AArch32
On 2015/12/7 21:56, Marc Zyngier wrote:
+static int kvm_arm_pmu_set_attr(struct kvm_device *dev,
>+ struct kvm_device_attr *attr)
>+{
>+ switch (attr->group) {
>+ case KVM_DEV_ARM_PMU_GRP_IRQ: {
>+ int __user *uaddr = (int __user *)(long)attr->addr;
>+
Hi Marc,
On 2015/12/7 22:11, Marc Zyngier wrote:
Shannon,
On 03/12/15 06:11, Shannon Zhao wrote:
From: Shannon Zhao
This patchset adds guest PMU support for KVM on ARM64. It takes
trap-and-emulate approach. When guest wants to monitor one event, it
will be trapped by KVM and KVM will call
Hi Marc,
On 2015/12/7 22:55, Marc Zyngier wrote:
> On 07/12/15 14:31, Shannon Zhao wrote:
>> >
>> >
>> > On 2015/12/7 22:06, Marc Zyngier wrote:
>>> >> On 03/12/15 06:11, Shannon Zhao wrote:
>>>> >>> From: Shannon Zhao
>&g
From: Shannon Zhao
Here we plan to support virtual PMU for guest by full software
emulation, so define some basic structs and functions preparing for
futher steps. Define struct kvm_pmc for performance monitor counter and
struct kvm_pmu for performance monitor unit for each vcpu. According to
From: Shannon Zhao
Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMOVSSET or PMOVSCLR register.
When writing non-zero value to PMOVSSET, pend PMU interrupt. When the
value writing to PMOVSCLR is equal to the
From: Shannon Zhao
Add access handler which emulates writing and reading PMEVTYPERn or
PMCCFILTR register. When writing to PMEVTYPERn or PMCCFILTR, call
kvm_pmu_set_counter_event_type to create a perf_event for the selected
event type.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c
From: Shannon Zhao
Add reset handler which gets host value of PMCEID0 or PMCEID1. Since
write action to PMCEID0 or PMCEID1 is ignored, add a new case for this.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 29 +
1 file changed, 25 insertions(+), 4
From: Shannon Zhao
Since the reset value of PMEVCNTRn or PMCCNTR is UNKNOWN, use
reset_unknown for its reset handler. Add access handler which emulates
writing and reading PMEVCNTRn or PMCCNTR register. When reading
PMEVCNTRn or PMCCNTR, call perf_event_read_value to get the count value
of the
From: Shannon Zhao
When resetting vcpu, it needs to reset the PMU state to initial status.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/reset.c | 3 +++
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c | 17 +
3 files changed, 22 insertions(+)
diff --git a/arch/arm64
From: Shannon Zhao
Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMCNTENSET or PMCNTENCLR register.
When writing to PMCNTENSET, call perf_event_enable to enable the perf
event. When writing to PMCNTENCLR
From: Shannon Zhao
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
disabled. When writing 1 to PMCR.P, reset all event counters, not
including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to
zero
From: Shannon Zhao
Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMINTENSET or PMINTENCLR register.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 28
1 file
From: Shannon Zhao
Add access handler which emulates writing and reading PMSWINC
register and add support for creating software increment event.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 16 +++-
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 44
From: Shannon Zhao
This patchset adds guest PMU support for KVM on ARM64. It takes
trap-and-emulate approach. When guest wants to monitor one event, it
will be trapped by KVM and KVM will call perf_event API to create a perf
event and call relevant perf_event APIs to get the count value of event
From: Shannon Zhao
The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c830fde..80b66c0
From: Shannon Zhao
Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
the kvm_device_ops for it.
Signed-off-by: Shannon Zhao
---
Documentation/virtual/kvm/devices/arm-pmu.txt | 16 +
arch/arm64/include/uapi/asm/kvm.h | 3 +
include/linux/kvm_host.h
From: Shannon Zhao
When calling perf_event_create_kernel_counter to create perf_event,
assign a overflow handler. Then when perf event overflows, call
kvm_vcpu_kick() to sync the interrupt.
Signed-off-by: Shannon Zhao
---
arch/arm/kvm/arm.c| 2 ++
include/kvm/arm_pmu.h | 2 ++
virt/kvm
From: Shannon Zhao
To use the ARMv8 PMU related register defines from the KVM code,
we move the relevant definitions to asm/pmu.h header file.
Signed-off-by: Anup Patel
Signed-off-by: Shannon Zhao
---
arch/arm64/include/asm/pmu.h | 64 ++
arch/arm64
From: Shannon Zhao
Add reset handler which gets host value of PMCR_EL0 and make writable
bits architecturally UNKNOWN except PMCR.E to zero. Add a common access
handler for PMU registers which emulates writing and reading register
and add emulation for PMCR.
Signed-off-by: Shannon Zhao
From: Shannon Zhao
We are about to trap and emulate accesses to each PMU register
individually. This adds the context offsets for the AArch64 PMU
registers and their AArch32 counterparts.
Signed-off-by: Shannon Zhao
---
arch/arm64/include/asm/kvm_asm.h | 45
From: Shannon Zhao
When we use tools like perf on host, perf passes the event type and the
id of this event type category to kernel, then kernel will map them to
hardware event number and write this number to PMU PMEVTYPER_EL0
register. When getting the event number in KVM, directly use raw
From: Shannon Zhao
Accessing PMXEVCNTR register is mapped to the PMEVCNTRn or PMCCNTR which
is selected by PMSELR.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 44 ++--
1 file changed, 42 insertions(+), 2 deletions(-)
diff --git a/arch
From: Shannon Zhao
Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. As it doesn't need to deal with the accessing action
specially, it uses default case to emulate writing and reading PMSELR
register.
Signed-off-by: Shannon Zhao
---
arch/arm6
From: Shannon Zhao
Accessing PMXEVTYPER register is mapped to the PMEVTYPERn or
PMCCFILTR which is selected by PMSELR. If the value of PMSELR is valid,
call kvm_pmu_set_counter_event_type to create a perf_event.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 55
From: Shannon Zhao
When KVM frees VCPU, it needs to free the perf_event of PMU.
Signed-off-by: Shannon Zhao
---
arch/arm/kvm/arm.c| 1 +
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 21 +
3 files changed, 24 insertions(+)
diff --git a/arch/arm/kvm/arm.c b
On 2015/12/8 22:10, Marc Zyngier wrote:
On 08/12/15 13:53, Will Deacon wrote:
On Tue, Dec 08, 2015 at 01:37:14PM +, Marc Zyngier wrote:
On 08/12/15 12:47, Shannon Zhao wrote:
From: Shannon Zhao
Here we plan to support virtual PMU for guest by full software
emulation, so define some
On 2015/12/8 23:43, Marc Zyngier wrote:
> On 08/12/15 12:47, Shannon Zhao wrote:
>> From: Shannon Zhao
>> +/**
>> + * kvm_pmu_get_counter_value - get PMU counter value
>> + * @vcpu: The vcpu pointer
>> + * @select_idx: The counter index
>> + */
>> +
On 2015/12/9 0:42, Marc Zyngier wrote:
>> +void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable)
>> > +{
>> > + int i;
>> > + struct kvm_pmu *pmu = &vcpu->arch.pmu;
>> > + struct kvm_pmc *pmc;
>> > +
>> > + if (!all_enable)
>> > + return;
> You have the vcpu. C
On 2015/12/9 0:59, Marc Zyngier wrote:
>> > + }
>> > +
>> > + /* If all overflow bits are cleared, kick the vcpu to clear interrupt
>> > + * pending status.
>> > + */
>> > + if (val == 0)
>> > + kvm_vcpu_kick(vcpu);
> Do we really need to do so? This will be dropped on the next en
On 2015/12/9 1:03, Marc Zyngier wrote:
> On 08/12/15 12:47, Shannon Zhao wrote:
>> > From: Shannon Zhao
>> >
>> > The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown.
>> >
>> > Signed-off-by: Shannon Zhao
>> > ---
>>
Hi Marc,
On 2015/12/9 0:30, Marc Zyngier wrote:
> On 08/12/15 12:47, Shannon Zhao wrote:
>> > From: Shannon Zhao
>> >
>> > Since the reset value of PMEVCNTRn or PMCCNTR is UNKNOWN, use
>> > reset_unknown for its reset handler. Add access handler which emul
On 2015/12/10 20:07, Marc Zyngier wrote:
> Hi Shannon,
>
> On 10/12/15 11:36, Shannon Zhao wrote:
>> > Hi Marc,
>> >
>> > On 2015/12/9 0:30, Marc Zyngier wrote:
>>> >> On 08/12/15 12:47, Shannon Zhao wrote:
>>>>> >>>>
From: Shannon Zhao
This patchset adds guest PMU support for KVM on ARM64. It takes
trap-and-emulate approach. When guest wants to monitor one event, it
will be trapped by KVM and KVM will call perf_event API to create a perf
event and call relevant perf_event APIs to get the count value of event
From: Shannon Zhao
When resetting vcpu, it needs to reset the PMU state to initial status.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/reset.c | 3 +++
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c | 17 +
3 files changed, 22 insertions(+)
diff --git a/arch/arm64
From: Shannon Zhao
When calling perf_event_create_kernel_counter to create perf_event,
assign a overflow handler. Then when the perf event overflows, set the
corresponding bit of guest PMOVSSET register. If this counter is enabled
and its interrupt is enabled as well, kick the vcpu to sync the
From: Shannon Zhao
Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMCNTENSET or PMCNTENCLR register.
When writing to PMCNTENSET, call perf_event_enable to enable the perf
event. When writing to PMCNTENCLR
From: Shannon Zhao
Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMINTENSET or PMINTENCLR register.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 29 +
1 file
From: Shannon Zhao
These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which
is mapped to PMEVCNTRn.
The access handler translates all aarch32 register offsets to aarch64
ones and uses vcpu_sys_reg() to access their values to avoid taking care
of big endian.
When reading these
From: Shannon Zhao
Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
the kvm_device_ops for it.
Signed-off-by: Shannon Zhao
---
Documentation/virtual/kvm/devices/arm-pmu.txt | 16
arch/arm64/include/uapi/asm/kvm.h | 3 +
include/linux/kvm_host.h
From: Shannon Zhao
The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown.
PMUSERENR_EL0 holds some bits which decide whether PMU registers can be
accessed from EL0. Add some check helpers to handle the access from EL0.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 124
From: Shannon Zhao
Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMOVSSET or PMOVSCLR register.
When writing non-zero value to PMOVSSET, pend PMU interrupt.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm
From: Shannon Zhao
Here we plan to support virtual PMU for guest by full software
emulation, so define some basic structs and functions preparing for
futher steps. Define struct kvm_pmc for performance monitor counter and
struct kvm_pmu for performance monitor unit for each vcpu. According to
From: Shannon Zhao
Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. When reading PMSELR, return the PMSELR.SEL field to
guest.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 17 +++--
1 file changed, 15 insertions(+), 2
From: Shannon Zhao
When we use tools like perf on host, perf passes the event type and the
id of this event type category to kernel, then kernel will map them to
hardware event number and write this number to PMU PMEVTYPER_EL0
register. When getting the event number in KVM, directly use raw
From: Shannon Zhao
These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
which is mapped to PMEVTYPERn or PMCCFILTR.
The access handler translates all aarch32 register offsets to aarch64
ones and uses vcpu_sys_reg() to access their values to avoid taking care
of big endian.
When
From: Shannon Zhao
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
disabled. When writing 1 to PMCR.P, reset all event counters, not
including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to
zero
From: Shannon Zhao
When KVM frees VCPU, it needs to free the perf_event of PMU.
Signed-off-by: Shannon Zhao
---
arch/arm/kvm/arm.c| 1 +
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 21 +
3 files changed, 24 insertions(+)
diff --git a/arch/arm/kvm/arm.c b
From: Shannon Zhao
Add access handler which gets host value of PMCEID0 or PMCEID1 when
guest access these registers. Writing action to PMCEID0 or PMCEID1 is
ignored.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 26 ++
1 file changed, 22 insertions(+), 4
From: Shannon Zhao
Add reset handler which gets host value of PMCR_EL0 and make writable
bits architecturally UNKNOWN except PMCR.E which is zero. Add an access
handler for PMCR.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 39 +--
1 file
From: Shannon Zhao
To use the ARMv8 PMU related register defines from the KVM code,
we move the relevant definitions to asm/pmu.h header file.
Signed-off-by: Anup Patel
Signed-off-by: Shannon Zhao
---
arch/arm64/include/asm/pmu.h | 64 ++
arch/arm64
From: Shannon Zhao
Add access handler which emulates writing and reading PMSWINC
register and add support for creating software increment event.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 14 +-
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 32
From: Shannon Zhao
We are about to trap and emulate accesses to each PMU register
individually. This adds the context offsets for the AArch64 PMU
registers.
Signed-off-by: Shannon Zhao
---
arch/arm64/include/asm/kvm_asm.h | 25 -
1 file changed, 20 insertions(+), 5
On 2015/12/15 19:34, Marc Zyngier wrote:
On 15/12/15 08:49, Shannon Zhao wrote:
From: Shannon Zhao
To use the ARMv8 PMU related register defines from the KVM code,
we move the relevant definitions to asm/pmu.h header file.
Signed-off-by: Anup Patel
Signed-off-by: Shannon Zhao
---
arch
On 2015/12/15 23:33, Marc Zyngier wrote:
On 15/12/15 08:49, Shannon Zhao wrote:
>From: Shannon Zhao
>
>Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
>the kvm_device_ops for it.
>
>Signed-off-by: Shannon Zhao
>---
> Documentation/virtual
On 2015/12/15 22:58, Marc Zyngier wrote:
On 15/12/15 08:49, Shannon Zhao wrote:
>From: Shannon Zhao
>
>The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown.
>
>PMUSERENR_EL0 holds some bits which decide whether PMU registers can be
>accessed from EL0. Add som
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