>From a9670ddff84080c56183e2d678189e100f891174 Mon Sep 17 00:00:00 2001
From: Liu, Jinsong
Date: Wed, 17 Aug 2011 11:36:28 +0800
Subject: [PATCH] KVM: emulate lapic tsc deadline timer for hvm
This patch emulate lapic tsc deadline timer for hvm:
Enumerate tsc deadline timer capacibility by CP
>From 728a17e2de591b557c3c8ba31076b4bf2ca5ab42 Mon Sep 17 00:00:00 2001
From: Liu, Jinsong
Date: Wed, 5 Sep 2012 03:18:15 +0800
Subject: [PATCH] KVM: tsc deadline timer works only when hrtimer high
resolution configured
This is for 2 reasons:
1. it's pointless to enable tsc deadline
Thanks Avi, Marcelo, Kevin for comments, sorry for late reply (just come back
from vacation).
Avi Kivity wrote:
> On 08/17/2011 07:19 AM, Liu, Jinsong wrote:
>> From a9670ddff84080c56183e2d678189e100f891174 Mon Sep 17 00:00:00
>> 2001
>> From: Liu, Jinsong
>> Date
Marcelo Tosatti wrote:
>>> --- a/arch/x86/include/asm/msr-index.h
>>> +++ b/arch/x86/include/asm/msr-index.h
>>> @@ -229,6 +229,8 @@
>>> #define MSR_IA32_APICBASE_ENABLE (1<<11)
>>> #define MSR_IA32_APICBASE_BASE (0xf<<12)
>>>
>>> +#define MSR_IA32_TSCDEADLINE 0x0
Avi Kivity wrote:
>>
>> --- a/arch/x86/include/asm/msr-index.h
>> +++ b/arch/x86/include/asm/msr-index.h
>> @@ -229,6 +229,8 @@
>> #define MSR_IA32_APICBASE_ENABLE (1<<11)
>> #define MSR_IA32_APICBASE_BASE (0xf<<12)
>>
>> +#define MSR_IA32_TSCDEADLINE0x06
Avi Kivity wrote:
> On 09/07/2011 07:45 PM, Liu, Jinsong wrote:
>> Avi Kivity wrote:
>>>>
>>>> --- a/arch/x86/include/asm/msr-index.h
>>>> +++ b/arch/x86/include/asm/msr-index.h
>>>> @@ -229,6 +229,8 @@
>>>&g
>>> --- a/arch/x86/include/asm/msr-index.h
>>> +++ b/arch/x86/include/asm/msr-index.h
>>> @@ -229,6 +229,8 @@
>>> #define MSR_IA32_APICBASE_ENABLE (1<<11)
>>> #define MSR_IA32_APICBASE_BASE (0xf<<12)
>>>
>>> +#define MSR_IA32_TSCDEADLINE 0x06e0
>>> +
>>> #def
Marcelo Tosatti wrote:
> On Fri, Sep 09, 2011 at 01:12:51AM +0800, Liu, Jinsong wrote:
>>>>> --- a/arch/x86/include/asm/msr-index.h
>>>>> +++ b/arch/x86/include/asm/msr-index.h
>>>>> @@ -229,6 +229,8 @@
>>>>> #define MSR_IA3
Marcelo Tosatti wrote:
> On Fri, Sep 09, 2011 at 01:12:51AM +0800, Liu, Jinsong wrote:
>>>>> --- a/arch/x86/include/asm/msr-index.h
>>>>> +++ b/arch/x86/include/asm/msr-index.h
>>>>> @@ -229,6 +229,8 @@
>>>>> #define MSR_IA3
>>
>> My question is, which kvm_get_msrs/kvm_put_msrs routine be used by
>> live migration, the routine in target-i386/kvm.c, or in
>> kvm/libkvm/libkvm-x86.c? They both have ioctl
>> KVM_GET_MSR_INDEX_LIST/ KVM_GET_MSRS/ KVM_SET_MSRS, but I'm not
>> clear their purpose/usage difference.
>
>
>From 7b12021e1d1b79797b49e41cc0a7be05a6180d9a Mon Sep 17 00:00:00 2001
From: Liu, Jinsong
Date: Tue, 13 Sep 2011 21:52:54 +0800
Subject: [PATCH] KVM: emulate lapic tsc deadline timer for guest
This patch emulate lapic tsc deadline timer for guest:
Enumerate tsc deadline timer capability
>From c1b502d6548fcc41592cd90acc82109ee949df75 Mon Sep 17 00:00:00 2001
From: Liu, Jinsong
Date: Tue, 13 Sep 2011 22:05:30 +0800
Subject: [PATCH] Qemu co-operation with kvm tsc deadline timer
KVM add emulation of lapic tsc deadline timer for guest.
This patch is co-operation work at qemu s
Jan Kiszka wrote:
> On 2011-09-13 16:38, Liu, Jinsong wrote:
>> From c1b502d6548fcc41592cd90acc82109ee949df75 Mon Sep 17 00:00:00
>> 2001
>> From: Liu, Jinsong
>> Date: Tue, 13 Sep 2011 22:05:30 +0800
>> Subject: [PATCH] Qemu co-operation with kvm tsc deadline
Marcelo Tosatti wrote:
>> diff --git a/arch/x86/include/asm/apicdef.h
>> b/arch/x86/include/asm/apicdef.h
>> index 34595d5..3925d80 100644
>> --- a/arch/x86/include/asm/apicdef.h
>> +++ b/arch/x86/include/asm/apicdef.h
>> @@ -100,7 +100,9 @@
>> #define APIC_TIMER_BASE_CLKIN
Marcelo Tosatti wrote:
>> +} else if (apic_lvtt_tscdeadline(apic)) {
>> +/* lapic timer in tsc deadline mode */
>> +u64 guest_tsc, guest_tsc_delta, ns = 0;
>> +struct kvm_vcpu *vcpu = apic->vcpu;
>> +unsigned long this_tsc_khz = vcpu_tsc_khz(vcpu)
>From cab4eb79efc498abbda19c5b10c7d0858349af5f Mon Sep 17 00:00:00 2001
From: Liu, Jinsong
Date: Thu, 22 Sep 2011 09:49:05 +0800
Subject: [PATCH 1/2] Add some pre-defination
This pre-defination is preparing for KVM tsc deadline timer emulation, but
theirself are no-kvm-specific.
Signed-off
>From 4d5b83aba40ce0d421add9a41a6c591a8590a32e Mon Sep 17 00:00:00 2001
From: Liu, Jinsong
Date: Thu, 22 Sep 2011 14:00:08 +0800
Subject: [PATCH 2/2] KVM: emulate lapic tsc deadline timer for guest
This patch emulate lapic tsc deadline timer for guest:
Enumerate tsc deadline timer capability
>From 8c39f2ddbf7069342826a83e535c0c7b641d6501 Mon Sep 17 00:00:00 2001
From: Liu, Jinsong
Date: Thu, 22 Sep 2011 16:28:13 +0800
Subject: [PATCH] Qemu co-operation with kvm tsc deadline timer
KVM add emulation of lapic tsc deadline timer for guest.
This patch is co-operation work at qemu s
Marcelo Tosatti wrote:
> On Thu, Sep 22, 2011 at 04:55:52PM +0800, Liu, Jinsong wrote:
>>> From 4d5b83aba40ce0d421add9a41a6c591a8590a32e Mon Sep 17 00:00:00
>>> 2001
>> From: Liu, Jinsong
>> Date: Thu, 22 Sep 2011 14:00:08 +0800
>> Subject: [PATCH 2/2] KV
Marcelo Tosatti wrote:
> On Thu, Sep 22, 2011 at 04:55:52PM +0800, Liu, Jinsong wrote:
>>> From 4d5b83aba40ce0d421add9a41a6c591a8590a32e Mon Sep 17 00:00:00
>>> 2001
>> From: Liu, Jinsong
>> Date: Thu, 22 Sep 2011 14:00:08 +0800
>> Subject: [PATCH 2/2] KV
>From 7b58c09d1bb70c7ca8aa29892b08ba4a3e7b9e92 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Sun, 25 Sep 2011 15:48:29 +0800
Subject: [PATCH] Qemu co-operation with kvm tsc deadline timer
KVM add emulation of lapic tsc deadline timer for guest.
This patch is co-operation work at qemu s
Marcelo Tosatti wrote:
> On Fri, Sep 23, 2011 at 04:25:51PM +0800, Liu, Jinsong wrote:
>> Marcelo Tosatti wrote:
>>> On Thu, Sep 22, 2011 at 04:55:52PM +0800, Liu, Jinsong wrote:
>>>>> From 4d5b83aba40ce0d421add9a41a6c591a8590a32e Mon Sep 17 00:00:00
>>>
Yes, Avi has noticed this issue and fix the bug as attached.
Thanks,
Jinsong
Dan Carpenter wrote:
> This patch causes a NULL dereference for me when I start qemu.
>
> [ 136.130978] BUG: unable to handle kernel NULL pointer dereference
> at 0078 [ 136.131032] IP: []
> update_cpuid+0
Marcelo Tosatti wrote:
> On Sun, Sep 25, 2011 at 10:47:46PM +0800, Liu, Jinsong wrote:
>> Marcelo Tosatti wrote:
>>> On Fri, Sep 23, 2011 at 04:25:51PM +0800, Liu, Jinsong wrote:
>>>> Marcelo Tosatti wrote:
>>>>> On Thu, Sep 22, 2011 at 04:55
out'
Do I miss something? how can I get test log?
Thanks,
Jinsong
==
>From 92d05a2caca4d0a35651bd06b88cf78b4e24d5b7 Mon Sep 17 00:00:00 2001
From: Liu, Jinsong
Date: Sun, 9 Oct 2011 17:16:17 +0800
Subject: [PATCH] apic: test tsc deadline timer
Test tsc deadline timer: de
Avi Kivity wrote:
> On 10/09/2011 12:05 PM, Liu, Jinsong wrote:
>> Marcelo,
>>
>> I add test case for tsc deadline timer
>> https://github.com/avikivity/kvm-unit-tests, as attached.
>>
>> According to the kvm-unit-tests README, I try to run
>> qemu-
Updated test case for kvm tsc deadline timer
https://github.com/avikivity/kvm-unit-tests, as attached.
Thanks,
Jinsong
=
>From 2b476cf741b36da5df35cf2e8f7f9562e8245fcd Mon Sep 17 00:00:00 2001
From: Liu, Jinsong
Date: Sun, 9 Oct 2011 22:45:39 +0800
Subject: [PATCH] apic: t
interrupt: PASS
> tsc deadline timer: PASS
> tsc deadline timer enabled
>
> summary: 5 tests, 0 failures
>
BTW, it better update kvm-unit-tests README.
Thanks,
Jinsong
=
>From ba2da790502f0ce2fb6dba9fc848cba041d051f8 Mon Sep 17 00:00:00 2001
From: Liu, Ji
Marcelo,
I just test guest migration from v13 to v12, it failed w/ info
savevm: unsupported version 13 for 'cpu' v12
load of migration failed
v13 is new qemu-kvm with tsc deadline timer co-work patch, v12 is old qemu-kvm.
Marcelo Tosatti wrote:
> Jinsong, please test this qemu-kvm patch by migr
Avi Kivity wrote:
> On 10/09/2011 05:32 PM, Liu, Jinsong wrote:
>> Updated test case for kvm tsc deadline timer
>> https://github.com/avikivity/kvm-unit-tests, as attached.
>>
>
> Applied, thanks.
Which tree? I didn't find it at git://github.com/avikivity/kvm
Marcelo Tosatti wrote:
> On Wed, Oct 12, 2011 at 12:26:12PM +0800, Liu, Jinsong wrote:
>> Marcelo,
>>
>> I just test guest migration from v13 to v12, it failed w/ info
>> savevm: unsupported version 13 for 'cpu' v12
>> load of migration failed
>>
>From 8bb5d052825149c211afa92458912bc49a50ee2f Mon Sep 17 00:00:00 2001
From: Liu, Jinsong
Date: Mon, 28 Nov 2011 03:55:19 -0800
Subject: [PATCH] X86: expose latest Intel cpu new features to guest
Intel latest cpu add 6 new features, refer http://software.intel.com/file/36945
The new feat
Avi Kivity wrote:
> On 12/21/2011 12:25 PM, Jan Kiszka wrote:
>> We must not report the TSC deadline timer feature on our own when
>> user space provides the APIC as we have no clue about its features.
>
> We must not report the TSC deadline timer feature on our own, period.
> We should just updat
Avi Kivity wrote:
> On 12/22/2011 05:41 PM, Liu, Jinsong wrote:
>> Avi Kivity wrote:
>>> On 12/21/2011 12:25 PM, Jan Kiszka wrote:
>>>> We must not report the TSC deadline timer feature on our own when
>>>> user space provides the APIC as we have no clu
Avi Kivity wrote:
> From: Jan Kiszka
>
> Unlike all of the other cpuid bits, the TSC deadline timer bit is set
> unconditionally, regardless of what userspace wants.
>
> This is broken in several ways:
> - if userspace doesn't use KVM_CREATE_IRQCHIP, and doesn't emulate
>the TSC deadline ti
Sasha Levin wrote:
> On Sun, 2011-12-25 at 21:00 +0200, Sasha Levin wrote:
>> On Sun, 2011-12-25 at 15:03 +0200, Avi Kivity wrote:
>>> + if (apic) {
>>> + if (best->ecx & bit(X86_FEATURE_TSC_DEADLINE_TIMER))
>>> + apic->lapic_timer.timer_mode_mask = 3 << 17;
>>> +
Avi Kivity wrote:
> On 12/26/2011 10:11 AM, Liu, Jinsong wrote:
>>>
>>> It breaks live migration: if you start a guest on a TSC-deadline
>>> capable host kernel, and migrate it to a TSC-deadline incapable host
>>> kernel, you end up with a broken guest.
&
>From 19caf1db1f93e6f6b736e1dfd5e91a0c7669adec Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Tue, 27 Dec 2011 04:08:27 +0800
Subject: [PATCH] Expose tsc deadline timer cpuid to guest
Depend on several factors:
1. Considering live migration, user enable/disable tsc deadline timer;
2. If gu
>> diff --git a/qemu-kvm.h b/qemu-kvm.h
>> index 2bd5602..8c6c2ea 100644
>> --- a/qemu-kvm.h
>> +++ b/qemu-kvm.h
>> @@ -260,6 +260,7 @@ extern int kvm_irqchip;
>> extern int kvm_pit;
>> extern int kvm_pit_reinject;
>> extern unsigned int kvm_shadow_memory;
>> +extern int tsc_deadline_timer;
>>
>From 5afecc308bc25c7fd8d124e7557f08fb067d6caa Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Thu, 29 Dec 2011 01:45:45 +0800
Subject: [PATCH 1/2] Define KVM_CAP_TSC_DEADLINE_TIMER
Signed-off-by: Liu, Jinsong
Signed-off-by: Jan Kiszka
---
linux-headers/linux/kvm.h |1 +
1 files chan
>From 3a78adf8006ec6189bfe2f55f7ae213e75bf3815 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Thu, 29 Dec 2011 05:28:12 +0800
Subject: [PATCH 2/2] Expose tsc deadline timer cpuid to guest
Depend on several factors:
1. Considering live migration, user enable/disable tsc deadline timer;
2.
Jan Kiszka wrote:
> On 2011-12-28 18:35, Liu, Jinsong wrote:
>>>> diff --git a/qemu-kvm.h b/qemu-kvm.h
>>>> index 2bd5602..8c6c2ea 100644
>>>> --- a/qemu-kvm.h
>>>> +++ b/qemu-kvm.h
>>>> @@ -260,6 +260,7 @@ extern int kvm_irqch
CPUID_EXT_TSC_DEADLINE_TIMER;
+}
+}
> - disable it for older machine types (see below) by default
>
> TSC deadline timer emulation in user space is a different story to be
> told once we have a patch for it.
>
>>
>> Signed-off-by: Liu, Jinsong ---
>>
Jan Kiszka wrote:
> On 2012-01-05 18:07, Liu, Jinsong wrote:
>>> Sorry, it remains bogus to expose the tsc deadline timer feature on
>>> machines < pc-1.1. That's just like we introduced kvmclock only to
>>> pc-0.14 onward. The reason is that guest OSes s
Eduardo, Jan
I will update tsc deadline timer patch (at qemu-kvm side) recently.
Have you made a final agreement of the issue 'KVM_CAP_TSC_DEADLINE_TIMER' vs.
'GET_SUPPORTED_CPUID'?
Thanks,
Jinsong
Eduardo Habkost wrote:
> (CCing Andre Przywara, in case he can help to clarify what's the
> expe
Eduardo Habkost wrote:
> On Thu, Jun 14, 2012 at 07:02:03PM +0000, Liu, Jinsong wrote:
>> Eduardo, Jan
>>
>> I will update tsc deadline timer patch (at qemu-kvm side) recently.
>> Have you made a final agreement of the issue
>> 'KVM_CAP_TSC_DEADLINE_TIMER
mails regarding to cpuid
exposing these days.
However, I think I may ignore something (so many discussion :-), so if you
think anything wrong, please point out to me.
Thanks,
Jinsong
>From 8b5b003f6f8834d2d5d71e18bb47b7f089bc4928 Mon Sep 17 00:00:00 2001
From: Liu, Jinsong
Date
Jan Kiszka wrote:
> On 2012-01-07 19:23, Liu, Jinsong wrote:
>> Jan Kiszka wrote:
>>> On 2012-01-05 18:07, Liu, Jinsong wrote:
>>>>> Sorry, it remains bogus to expose the tsc deadline timer feature
>>>>> on machines < pc-1.1. That's just
>From ecd8be962f69393c183f941bfdbd7a7d3876d442 Mon Sep 17 00:00:00 2001
From: Liu, Jinsong
Date: Mon, 27 Feb 2012 05:19:32 +0800
Subject: [PATCH] KVM: expose Intel cpu new features to guest
Intel recently release 2 new features, HLE and TRM.
Refer to http://software.intel.com/file/41417.
T
ser to control the feature exposing via a cpu feature flag.
Signed-off-by: Liu, Jinsong
---
target-i386/cpu.h |1 +
target-i386/cpuid.c |2 +-
target-i386/kvm.c |4
3 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index d9
Avi,
Any comments?
Thanks,
Jinsong
Liu, Jinsong wrote:
> From ecd8be962f69393c183f941bfdbd7a7d3876d442 Mon Sep 17 00:00:00 2001
> From: Liu, Jinsong
> Date: Mon, 27 Feb 2012 05:19:32 +0800
> Subject: [PATCH] KVM: expose Intel cpu new features to guest
>
> Intel recently rele
Jan,
Any comments? I feel some confused about your point 'disable cpuid feature for
older machine types by default': are you planning a common approach for this
common issue, or, you just ask me a specific solution for the tsc deadline
timer case?
Thanks,
Jinsong
Liu, Jinsong wr
Jan Kiszka wrote:
> On 2012-03-06 08:49, Liu, Jinsong wrote:
>> Jan,
>>
>> Any comments? I feel some confused about your point 'disable cpuid
>> feature for older machine types by default': are you planning a
>> common approach for this common issue, or,
Jan Kiszka wrote:
> On 2012-03-09 19:27, Liu, Jinsong wrote:
>> Jan Kiszka wrote:
>>> On 2012-03-06 08:49, Liu, Jinsong wrote:
>>>> Jan,
>>>>
>>>> Any comments? I feel some confused about your point 'disable cpuid
>>>> feat
Liu, Jinsong wrote:
> Jan Kiszka wrote:
>> On 2012-03-06 08:49, Liu, Jinsong wrote:
>>> Jan,
>>>
>>> Any comments? I feel some confused about your point 'disable cpuid
>>> feature for older machine types by default': are you planning a
>
Jan Kiszka wrote:
> On 2012-03-09 20:09, Liu, Jinsong wrote:
>> Jan Kiszka wrote:
>>> On 2012-03-09 19:27, Liu, Jinsong wrote:
>>>> Jan Kiszka wrote:
>>>>> On 2012-03-06 08:49, Liu, Jinsong wrote:
>>>>>> Jan,
>>>>>>
Eduardo Habkost wrote:
> On Tue, Mar 20, 2012 at 12:53:57PM +0000, Liu, Jinsong wrote:
>> Rik van Riel wrote:
>>> On 03/09/2012 01:27 PM, Liu, Jinsong wrote:
>>>
>>>> As for 'tsc deadline' feature exposing, my patch (as attached) just
>&
Eduardo Habkost wrote:
> On Fri, Mar 23, 2012 at 03:49:27AM +0000, Liu, Jinsong wrote:
>> Eduardo Habkost wrote:
>>> [1] From Documentation/virtual/kvm/api.txt:
>>>
>>> "KVM_GET_SUPPORTED_CPUID
>>> [...]
>>> This ioctl returns x86 cpui
Eduardo Habkost wrote:
> On Fri, Mar 09, 2012 at 09:52:29PM +0100, Jan Kiszka wrote:
>> On 2012-03-09 20:09, Liu, Jinsong wrote:
>>> Jan Kiszka wrote:
>>>> On 2012-03-09 19:27, Liu, Jinsong wrote:
>>>>> Jan Kiszka wrote:
>>>&g
>From 1273f8b2e5464ec987facf9942fd3ccc0b69087e Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Mon, 19 Aug 2013 09:33:30 +0800
Subject: [PATCH] qemu-kvm bugfix for IA32_FEATURE_CONTROL
This patch is to fix the bug https://bugs.launchpad.net/qemu-kvm/+bug/1207623
IA32_FEATURE_CONTROL
>From 1273f8b2e5464ec987facf9942fd3ccc0b69087e Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Mon, 19 Aug 2013 09:33:30 +0800
Subject: [PATCH] qemu-kvm bugfix for IA32_FEATURE_CONTROL
This patch is to fix the bug https://bugs.launchpad.net/qemu-kvm/+bug/1207623
IA32_FEATURE_CONTROL
Paolo Bonzini wrote:
>
> The patch looks good. Please repost it with checkpatch.pl failures
> fixed.
>
> Paolo
Thanks Stefan and Paolo! Updated patch attached.
Regards,
Jinsong
===
>From a0ddf948d40e42de862543157a5668a1c12faae6 Mon Sep 17 00:00:00 2001
From:
Andreas Färber wrote:
> Am 19.08.2013 16:31, schrieb Liu, Jinsong:
>> Paolo Bonzini wrote:
>>>
>>> The patch looks good. Please repost it with checkpatch.pl failures
>>> fixed.
>>>
>>> Paolo
>>
>> Thanks St
Paolo Bonzini wrote:
> Il 19/08/2013 16:59, Andreas Färber ha scritto:
>> qemu-kvm is no longer maintained since 1.3 so it should not be
>> occurring any more.
>>
>> Please use a prefix of "target-i386: " (the directory name) to signal
>> where you are changing code, i.e. x86 only.
>>
>> "bugfix
Intel has released new version of Intel Architecture Instruction Set
Extensions Programming Reference, adding new features like AVX-512,
MPX, etc. Refer to
http://download-software.intel.com/sites/default/files/319433-015.pdf
These 2 patches are prepare patches at qemu side to support Intel MPX fe
>From e4b58c7bafc4d9f913a572a1b1cfee91c92f1637 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Fri, 22 Nov 2013 00:24:16 +0800
Subject: [PATCH 1/2] target-i386: fix cpuid leaf 0x0d
Fix cpuid leaf 0x0d which incorrectly parsed eax and ebx.
Signed-off-by: Liu Jinsong
---
target-i386/cp
>From aac033473bc88befe39a9add99820c0a7118ac90 Mon Sep 17 00:00:00 2001
From: root
Date: Fri, 22 Nov 2013 00:24:35 +0800
Subject: [PATCH 2/2] target-i386: Intel MPX support
Expose cpuid leaf (0xd, 3) and (0xd, 4) to guest.
Fix ebx and re-calculate ecx of cpuid leaf (0xd, 0).
Signed-off-by:
Intel has released new version of Intel Architecture Instruction Set
Extensions Programming Reference, adding new features like AVX-512,
MPX, etc. Refer to
http://download-software.intel.com/sites/default/files/319433-015.pdf
These patches are to support Intel MPX for KVM.
PATCH 1/4 is some MPX de
>From 3a1a011100b38a275d8c95468c12c483e316bb15 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Fri, 29 Nov 2013 01:27:00 +0800
Subject: [PATCH 1/4] X86: Intel MPX definiation
Signed-off-by: Xudong Hao
Reviewed-by: Liu Jinsong
---
arch/x86/include/asm/cpufeature.h |2 ++
arch/x86/incl
>From b060be65e466291c91963e58c4880ec614d0b294 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Fri, 29 Nov 2013 01:27:53 +0800
Subject: [PATCH 2/4] KVM/X86: Fix xsave cpuid exposing bug
EBX of cpuid(0xD, 0) is dynamic per XCR0 features enable/disable.
Bit 63 of XCR0 is reserved for fut
>From 11ae33723027c7b8e53a8c109f127800d7f0ad6e Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Fri, 29 Nov 2013 01:28:19 +0800
Subject: [PATCH 3/4] KVM/X86: Enable Intel MPX for guest
Enable Intel Memory Protection Extension for guest.
Signed-off-by: Xudong Hao
Reviewed-by: Liu Jins
>From 7532bdffe9f74db65f6eff733cb227a66bef932e Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Sat, 30 Nov 2013 00:27:02 +0800
Subject: [PATCH 4/4] KVM/X86: Intel MPX vmx and msr handle
Signed-off-by: Xudong Hao
Reviewed-by: Liu Jinsong
---
arch/x86/include/asm/vmx.h|
Paolo Bonzini wrote:
> Il 29/11/2013 14:15, Liu, Jinsong ha scritto:
>> From e4b58c7bafc4d9f913a572a1b1cfee91c92f1637 Mon Sep 17 00:00:00
>> 2001
>> From: Liu Jinsong
>> Date: Fri, 22 Nov 2013 00:24:16 +0800
>> Subject: [PATCH 1/2] target-i386: fix cpuid lea
Paolo Bonzini wrote:
> Il 29/11/2013 14:17, Liu, Jinsong ha scritto:
>> From aac033473bc88befe39a9add99820c0a7118ac90 Mon Sep 17 00:00:00
>> 2001
>> From: root
>> Date: Fri, 22 Nov 2013 00:24:35 +0800
>> Subject: [PATCH 2/2] target-i386: Intel MPX support
>
Paolo Bonzini wrote:
>> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
>> index a8ce117..e30d4ce 100644
>> --- a/arch/x86/kvm/cpuid.c
>> +++ b/arch/x86/kvm/cpuid.c
>> @@ -75,7 +75,7 @@ void kvm_update_cpuid(struct kvm_vcpu *vcpu)
>> (best->eax | ((u64)best->edx << 32)
>From 57751d87392d7ee9df5698bc83b356de654453ef Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Tue, 3 Dec 2013 04:17:50 +0800
Subject: [PATCH 1/2] target-i386: fix cpuid leaf 0x0d
Fix cpuid leaf 0x0d which incorrectly parsed eax and ebx.
However, before this patch the CPUID worked fine --
>From 1a199d68265ffeb0234530f29d92a00a5edeff75 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Tue, 3 Dec 2013 05:08:19 +0800
Subject: [PATCH 2/2] target-i386: Intel MPX
Add some MPX related definiation, and hardcode sizes and offsets
of xsave features 3 and 4.
Signed-off-by: Liu Jins
>From fbfa537f690eca139a96c6b2636ab5130bf57716 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Fri, 29 Nov 2013 01:27:00 +0800
Subject: [PATCH 1/4] X86: Intel MPX definiation
Signed-off-by: Xudong Hao
Signed-off-by: Liu Jinsong
---
arch/x86/include/asm/cpufeature.h |2 ++
arch/
>From 4a2eb0a8467b4f278e59d2df209a1bc03349d088 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Tue, 3 Dec 2013 06:28:20 +0800
Subject: [PATCH 2/4] KVM/X86: Fix xsave cpuid exposing bug
EBX of cpuid(0xD, 0) is dynamic per XCR0 features enable/disable.
Bit 63 of XCR0 is reserved for fut
>From e9ba40b3d1820b8ab31431c73226ee3ed485edd1 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Tue, 3 Dec 2013 07:02:27 +0800
Subject: [PATCH 3/4] KVM/X86: Intel MPX vmx and msr handle
Signed-off-by: Xudong Hao
Signed-off-by: Liu Jinsong
---
arch/x86/include/asm/vmx.h|
>From 62553aebb7b72f1203fefc59dd4d8969e4216ddb Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Tue, 3 Dec 2013 07:34:32 +0800
Subject: [PATCH 4/4] KVM/X86: Enable Intel MPX for guest
Signed-off-by: Xudong Hao
Signed-off-by: Liu Jinsong
---
arch/x86/kvm/cpuid.c |2 +-
arch/x86/kvm/x8
Paolo Bonzini wrote:
> Il 02/12/2013 17:42, Liu, Jinsong ha scritto:
>> From 1a199d68265ffeb0234530f29d92a00a5edeff75 Mon Sep 17 00:00:00
>> 2001 From: Liu Jinsong
>> Date: Tue, 3 Dec 2013 05:08:19 +0800
>> Subject: [PATCH 2/2] target-i386: Intel MPX
>>
>>
Intel has released Memory Protection Extensions (MPX) recently.
Please refer to
http://download-software.intel.com/sites/default/files/319433-015.pdf
These 2 patches are version2 to support Intel MPX at qemu side.
Version 1:
* Fix cpuid leaf 0x0d bug which incorrectly parsed eax and ebx;
* Expose
>From cb3b12dd9873929b3a03214e3aa0ee5297e75119 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Tue, 3 Dec 2013 04:17:50 +0800
Subject: [PATCH v2 1/2] target-i386: fix cpuid leaf 0x0d
Fix cpuid leaf 0x0d which incorrectly parsed eax and ebx.
However, before this patch the CPUID worked f
>From 256484fd75d4eb4d248e5e0f493f16182da59dc2 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Wed, 4 Dec 2013 16:56:49 +0800
Subject: [PATCH v2 2/2] target-i386: Intel MPX
Add some MPX related definiation, and hardcode sizes and offsets
of xsave features 3 and 4. It also add corresponding p
>
> Almost there. Migration (vmstate) is still missing.
>
Like this:
==
>From faead85c0dbe62da896e0ed9e165d98e10216968 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Wed, 4 Dec 2013 16:56:49 +0800
Subject: [PATCH 2/2] target-i386: Intel MPX
Add some MPX related
Paolo Bonzini wrote:
> Il 04/12/2013 12:30, Liu, Jinsong ha scritto:
>>>>
>>>> Almost there. Migration (vmstate) is still missing.
>>>>
>> Like this:
>>
>> ==
>> From faead85c0dbe62da896e0ed9e165d98e10216968 Mon Sep
Intel has released Memory Protection Extensions (MPX) recently.
Please refer to
http://download-software.intel.com/sites/default/files/319433-015.pdf
These 2 patches are version2 to support Intel MPX at qemu side.
Version 1:
* Fix cpuid leaf 0x0d bug which incorrectly parsed eax and ebx;
* Expose
>From ee8b72df3b5503514b748035e6b1cb4d61f8e701 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Thu, 5 Dec 2013 08:32:12 +0800
Subject: [PATCH v3 1/2] target-i386: Intel MPX
Add some MPX related definiation, and hardcode sizes and offsets
of xsave features 3 and 4. It also add corresponding p
>From 12fa3564b7342c4e034b13671dc922ff23ac4b1e Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Sat, 7 Dec 2013 05:18:35 +0800
Subject: [PATCH v3 2/2] target-i386: MSR_IA32_BNDCFGS handle
Signed-off-by: Liu Jinsong
---
target-i386/cpu.h |3 +++
target-i386/kvm.c |
Paolo Bonzini wrote:
> Il 02/12/2013 17:46, Liu, Jinsong ha scritto:
>> From e9ba40b3d1820b8ab31431c73226ee3ed485edd1 Mon Sep 17 00:00:00
>> 2001
>> From: Liu Jinsong
>> Date: Tue, 3 Dec 2013 07:02:27 +0800
>> Subject: [PATCH 3/4] KVM/X86: Intel MPX vmx an
Eric Blake wrote:
> On 12/06/2013 07:06 AM, Liu, Jinsong wrote:
>> Intel has released Memory Protection Extensions (MPX) recently.
>> Please refer to
>> http://download-software.intel.com/sites/default/files/319433-015.pdf
>>
>> These 2 patches are version2
Paolo Bonzini wrote:
> Il 06/12/2013 15:06, Liu, Jinsong ha scritto:
>> Intel has released Memory Protection Extensions (MPX) recently.
>> Please refer to
>> http://download-software.intel.com/sites/default/files/319433-015.pdf
>>
>> These 2 patches are version2
Paolo Bonzini wrote:
> Il 07/12/2013 01:20, Qiaowei Ren ha scritto:
>> This patch defines xstate feature and extends struct xsave_hdr_struct
>> to support Intel MPX.
>>
>> Signed-off-by: Qiaowei Ren
>> Signed-off-by: Xudong Hao
>> Signed-off-by: Liu J
H. Peter Anvin wrote:
> On 12/06/2013 12:05 PM, Liu, Jinsong wrote:
>>>
>>> Since Peter already said the same, please undo these changes.
>>>
>>> Also, how is XSTATE_EAGER used? Should MPX be disabled when
>>> xsaveopt is disabled on the kernel co
Paolo, comments for version 2?
Thanks,
Jinsong
Liu, Jinsong wrote:
> These patches are version 2 to enalbe Intel MPX for KVM.
>
> Version 1:
> * Add some Intel MPX definiation
> * Fix a cpuid(0x0d, 0) exposing bug, dynamic per XCR0 features
> enable/disable
> * vmx a
Paolo Bonzini wrote:
> Il 11/12/2013 09:31, Liu, Jinsong ha scritto:
>> Paolo, comments for version 2?
>
> I think I commented that it's fine, I'm just waiting for a rebase on
> top of the generic patches.
>
> Paolo
>
Thanks! common MPX definiation patche
Paolo Bonzini wrote:
> Il 12/12/2013 06:47, Liu, Jinsong ha scritto:
>> Paolo Bonzini wrote:
>>> Il 11/12/2013 09:31, Liu, Jinsong ha scritto:
>>>> Paolo, comments for version 2?
>>>
>>> I think I commented that it's fine, I'm j
Paolo Bonzini wrote:
> Il 12/12/2013 12:09, Liu, Jinsong ha scritto:
>> Paolo Bonzini wrote:
>>> Il 12/12/2013 06:47, Liu, Jinsong ha scritto:
>>>> Paolo Bonzini wrote:
>>>>> Il 11/12/2013 09:31, Liu, Jinsong ha scritto:
>>>>>> Paolo
Paolo Bonzini wrote:
> Il 21/01/2014 16:25, Liu, Jinsong ha scritto:
>> Hmm? I remember I have sent out the rebased patches v3 last month
>> If you didn't receive them I'm OK to rebase and resend them. BTW,
>> what's the review remarks? I remember you comment
1 - 100 of 149 matches
Mail list logo
