On 10/22/2015 4:45 AM, Alexander Duyck wrote:
+/* Record states hold by PF */
+memcpy(&state->vf_data, &adapter->vfinfo[vfn], sizeof(struct
vf_data_storage));
+
+vf_shift = vfn % 32;
+reg_offset = vfn / 32;
+
+reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
+reg &= ~(1
On Thu, Oct 22, 2015 at 1:07 AM, Sasha Levin wrote:
> On 10/19/2015 11:15 AM, Dmitry Vyukov wrote:
>> On Mon, Oct 19, 2015 at 5:08 PM, Sasha Levin wrote:
>>> > On 10/19/2015 10:47 AM, Dmitry Vyukov wrote:
> >>> Right, the memory areas that are accessed both by the hypervisor and
> >>> th
On 21/10/2015 19:07, Sasha Levin wrote:
> On 10/19/2015 11:15 AM, Dmitry Vyukov wrote:
>> But still: if result of a racy read is passed to guest, that can leak
>> arbitrary host data into guest.
>
> I see what you're saying.
I don't... how can it leak arbitrary host data? The memcpy cannot wri
On 10/25/2015 11:19 AM, Paolo Bonzini wrote:
>
>
> On 21/10/2015 19:07, Sasha Levin wrote:
>> On 10/19/2015 11:15 AM, Dmitry Vyukov wrote:
>>> But still: if result of a racy read is passed to guest, that can leak
>>> arbitrary host data into guest.
>>
>> I see what you're saying.
>
> I don't...
https://bugzilla.kernel.org/show_bug.cgi?id=102301
Balázs László Batári changed:
What|Removed |Added
CC||b...@bayi.hu
--- Comment #2 from
On Fri, Oct 23, 2015 at 12:45:13PM -0200, Eduardo Habkost wrote:
> On Fri, Oct 23, 2015 at 10:27:27AM +0800, Haozhong Zhang wrote:
> > On Thu, Oct 22, 2015 at 04:45:21PM -0200, Eduardo Habkost wrote:
> > > On Tue, Oct 20, 2015 at 03:22:51PM +0800, Haozhong Zhang wrote:
> > > > This patchset enables
On Fri, Oct 23, 2015 at 12:58:02PM -0200, Eduardo Habkost wrote:
> On Fri, Oct 23, 2015 at 11:14:48AM +0800, Haozhong Zhang wrote:
> > On Thu, Oct 22, 2015 at 04:11:37PM -0200, Eduardo Habkost wrote:
> > > On Tue, Oct 20, 2015 at 03:22:54PM +0800, Haozhong Zhang wrote:
> > > > Set vcpu's TSC rate t
Test bit 0(LBR), bit 1(BTF) and bit 11(FREEZE_LBRS_ON_PMI)
of MSR_IA32_DEBUGCTLMSR register.
Bit 11 depends on bit 0, so I tested five combinations:
(1) bit 0
(2) bit 1
(3) bit 0 | bit 1
(4) bit 0 | bit 11
(5) bit 0 | bit 1 | bit 11
Pentium4, Atom and Skylake are not defined in Qemu.
I have tested
Paolo,
Here is my current patch queue for KVM on PPC. There's nothing much
in the way of new features this time; it's mostly bug fixes, plus
Nikunj has implemented support for KVM_CAP_NR_MEMSLOTS. These are
intended for the "next" branch of the KVM tree. Please pull.
Thanks,
Paul.
The followi
On Fri, Oct 16, 2015 at 08:41:31AM +0200, Thomas Huth wrote:
> Yes, we'll likely need this soon! 32 slots are not enough...
Would anyone object if I raised the limit for PPC to 512 slots?
Would that cause problems on embedded PPC, for instance?
Paul.
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On 2015年10月24日 02:36, Alexander Duyck wrote:
> I was thinking about it and I am pretty sure the dummy write approach is
> problematic at best. Specifically the issue is that while you are
> performing a dummy write you risk pulling in descriptors for data that
> hasn't been dummy written to yet.
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