Linus,
The following changes since commit 9bdc771f2c29a11920f477fba05a58e23ee42554:
Merge tag 'acpica-4.2-rc1' of
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm (2015-07-02
17:11:28 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/virt/kvm/kvm.gi
Allow a nested hypervisor to single step its guests.
Signed-off-by: Mihai Donțu
---
This patch applies on top of current linux-next.
---
arch/x86/include/asm/vmx.h | 1 +
arch/x86/include/uapi/asm/vmx.h | 2 ++
arch/x86/kvm/vmx.c | 10 +-
3 files changed, 12 inserti
On Wed, Jun 24, 2015 at 08:30:26PM -0700, Mario Smarduch wrote:
> Define the required kvm_vcpu_arch fields, and offsets to manage VFP state. And
> declary Hyp interface function to switch VFP registers.
>
>
> Signed-off-by: Mario Smarduch
> ---
> arch/arm/include/asm/kvm_asm.h |1 +
> arch
On Wed, Jun 24, 2015 at 08:30:27PM -0700, Mario Smarduch wrote:
> This patch implements the VFP context switch code called from vcpu_put in
> Host KVM. In addition it implements the logic to skip setting a VFP trap if
> one
> is not needed. Also resets the flag if Host KVM switched registers to tr
On Wed, Jun 24, 2015 at 08:30:28PM -0700, Mario Smarduch wrote:
> This patch implements host KVM interface to Hyp mode VFP function to
> switch out guest and switch in host.
>
> Signed-off-by: Mario Smarduch
> ---
> arch/arm/kvm/arm.c | 15 +++
> 1 file changed, 15 insertions(+)
>
Hi Mario,
On Wed, Jun 24, 2015 at 08:30:25PM -0700, Mario Smarduch wrote:
> Currently we do a lazy VFP switch in Hyp mode, but once we exit and re-enter
> hyp
> mode we trap again on VFP access. This mode has shown around 30-50%
> improvement
> running hackbench and lmbench.
>
> This patch seri
On Mon, Jun 29, 2015 at 05:37:10PM +0200, Eric Auger wrote:
> With the advent of GICv3 ITS in-kernel emulation, KVM GSI routing
> appears to be requested. More specifically MSI routing is needed.
> irqchip routing does not sound to be really useful on arm but usage of
> MSI routing also mandates to
On 2015/7/3 19:23, Paolo Bonzini wrote:
On 03/07/2015 10:56, Tiejun Chen wrote:
After commit 1cde2930e154 ("sched/preempt: Add static_key() to
preempt_notifiers") is introduced, preempt_notifier_{register, unregister}
always hold a mutex, jump_label_mutex. So in current case this shouldn't
work
From: Shannon Zhao
This patchset adds guest PMU support for KVM on ARM64. It takes
trap-and-emulate approach. When guest wants to monitor one event, it
will be trapped by KVM and KVM will call perf_event API to create a perf
event and call relevant perf_event APIs to get the count value of event.
From: Shannon Zhao
We are about to trap and emulate acccesses to each PMU register
individually. This adds the context offsets for the AArch64 PMU
registers and their AArch32 counterparts.
Signed-off-by: Shannon Zhao
---
arch/arm64/include/asm/kvm_asm.h | 59 +++
From: Shannon Zhao
Here we plan to support virtual PMU for guest by full software
emulation, so define some basic structs and functions preparing for
futher steps. Define struct kvm_pmc for performance monitor counter and
struct kvm_pmu for performance monitor unit for each vcpu. According to
ARM
From: Shannon Zhao
To use the ARMv8 PMU related register defines from the KVM code,
we move the relevant definitions to asm/pmu.h header file.
Signed-off-by: Anup Patel
Signed-off-by: Shannon Zhao
---
arch/arm64/include/asm/pmu.h | 45 ++
arch/arm64/k
From: Shannon Zhao
Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. Add access handler which emulates writing and reading
PMSELR_EL0 register.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 26 +-
1 file changed, 25 i
From: Shannon Zhao
Add access handler which emulates writing and reading PMSWINC_EL0
register and add support for creating software increment event.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 15 ++-
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 20
From: Shannon Zhao
Since the reset value of PMOVSSET_EL0 and PMOVSCLR_EL0 is UNKNOWN, use
reset_unknown for its reset handler. Add access handler which emulates
writing and reading PMOVSSET_EL0 or PMOVSCLR_EL0 register.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 30 +++
From: Shannon Zhao
Since the reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. Add access handler which emulates writing and reading
PMUSERENR_EL0 register.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 15 ++-
include/kvm/arm_pmu.h
From: Shannon Zhao
Since the reset value of PMCCNTR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. Add access handler which emulates writing and reading
PMCCNTR_EL0 register.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 19 ++-
1 file changed, 18 insert
From: Shannon Zhao
Since the reset value of PMXEVTYPER_EL0 is UNKNOWN, use reset_unknown
for its reset handler. Add access handler which emulates writing and
reading PMXEVTYPER_EL0 register. When writing to PMXEVTYPER_EL0, call
kvm_pmu_set_counter_event_type create a perf event for the selected
e
From: Shannon Zhao
Add KVM_CAP_ARM_PMU for userspace to check whether KVM supports PMU. Add
KVM_ARM_PMU_SET_IRQ for userspace to set PMU IRQ number.
Signed-off-by: Shannon Zhao
---
arch/arm/kvm/arm.c | 8
include/kvm/arm_pmu.h| 5 +
include/uapi/linux/kvm.h | 4
vir
From: Shannon Zhao
Add access handler which emulates writing and reading PMEVCNTRn_EL0 and
PMEVTYPERn_EL0.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 106 ++
1 file changed, 106 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b
From: Shannon Zhao
Since the reset value of PMXEVTYPER_EL0 is UNKNOWN, use reset_unknown
for its reset handler. Add access handler which emulates writing and
reading PMXEVTYPER_EL0 register. When reading PMXEVCNTR_EL0, call
perf_event_read_value to get the count value of the perf event.
Signed-o
From: Shannon Zhao
Add reset handler which gets host value of PMCEID0_EL0 or PMCEID1_EL0.
Add access handler which emulates writing and reading PMCEID0_EL0 or
PMCEID1_EL0 register.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 36 ++--
1 file chang
From: Shannon Zhao
Add reset handler which gets host value of PMCR_EL0 and make writable
bits architecturally UNKNOWN. Add access handler which emulates
writing and reading PMCR_EL0 register.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 41 +++
From: Shannon Zhao
When calling perf_event_create_kernel_counter to create perf_event,
assign a overflow handler. Then when perf event overflows, if vcpu
doesn't run, call irq_work_queue to wake up vcpu. Otherwise call
kvm_vgic_inject_irq to inject the interrupt.
Signed-off-by: Shannon Zhao
---
From: Shannon Zhao
Since the reset value of PMINTENSET_EL1 and PMINTENCLR_EL1 is UNKNOWN,
use reset_unknown for its reset handler. Add access handler which
emulates writing and reading PMINTENSET_EL1 or PMINTENCLR_EL1 register.
When writing to PMINTENSET_EL1, set the interrupt flag true. While
wr
From: Shannon Zhao
When we use tools like perf on host, perf passes the event type and the
id in this type category to kernel, then kernel will map them to event
number and write this number to PMU PMEVTYPER_EL0 register. While
we're trapping and emulating guest accesses to PMU registers, we get
From: Shannon Zhao
Since the reset value of PMCNTENSET_EL0 and PMCNTENCLR_EL0 is UNKNOWN,
use reset_unknown for its reset handler. Add access handler which
emulates writing and reading PMCNTENSET_EL0 or PMCNTENCLR_EL0 register.
When writing to PMCNTENSET_EL0, call perf_event_enable to enable the
Hello!
> I like this approach, but it runs into problems:
> As you read above the current documentation says that the flags field
> must be zero and the current KVM_SET_GSI_ROUTING handler bails out if it
> isn't. So userland would need to know whether it's safe to set that
> field.
This proble
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