Re: [PATCH v4 03/25] virtio-pci: move freeze/restore to virtio core

is patch landed in today's linux-next (next-20141015). > include/linux/virtio.h | 6 + > drivers/virtio/virtio.c | 54 > + > drivers/virtio/virtio_pci.c | 54 > ++--- > 3 file

Re: [PATCH net-next RFC 0/3] virtio-net: Conditionally enable tx interrupt

On 10/15/2014 07:06 AM, Michael S. Tsirkin wrote: > On Tue, Oct 14, 2014 at 02:53:27PM -0400, David Miller wrote: >> > From: Jason Wang >> > Date: Sat, 11 Oct 2014 15:16:43 +0800 >> > >>> > > We free old transmitted packets in ndo_start_xmit() currently, so any >>> > > packet must be orphaned als

Re: [patch 3/4] KVM: MMU: reload request from GET_DIRTY_LOG path

On Mon, Oct 13, 2014 at 05:52:38AM -0300, Marcelo Tosatti wrote: > On Fri, Oct 10, 2014 at 04:09:29PM +0300, Gleb Natapov wrote: > > On Wed, Oct 08, 2014 at 04:22:31PM -0300, Marcelo Tosatti wrote: > > > > > > > > > > Argh, lets try again: > > > > > > > > > > skip_pinned = true > > > > >

Re: [PATCH v11 1/6] KVM: Add architecture-specific TLB flush implementations

On 23.09.14 02:54, Mario Smarduch wrote: > Add support to declare architecture specific TLB flush function, for now > ARMv7. > > Signed-off-by: Mario Smarduch > --- > include/linux/kvm_host.h |1 + > virt/kvm/Kconfig |3 +++ > virt/kvm/kvm_main.c |4 > 3 files ch

Re: [PATCH v11 2/6] KVM: Add generic implementation of kvm_vm_ioctl_get_dirty_log

On 23.09.14 02:54, Mario Smarduch wrote: > Add support for generic implementation of dirty log read function. For now > x86_64 and ARMv7 share generic dirty log read. Other architectures call > their architecture specific functions. > > Signed-off-by: Mario Smarduch > --- > arch/arm/kvm/Kconfi

[PATCH v2] target-ppc: kvm: Fix memory overflow issue about strncat()

strncat() will append additional '\0' to destination buffer, so need additional 1 byte for it, or may cause memory overflow, just like other area within QEMU have done. And can use g_strdup_printf() instead of strncat(), which may be more easier understanding. Signed-off-by: Chen Gang --- targe

Re: [PATCH v2] target-ppc: kvm: Fix memory overflow issue about strncat()

On 15.10.14 15:48, Chen Gang wrote: > strncat() will append additional '\0' to destination buffer, so need > additional 1 byte for it, or may cause memory overflow, just like other > area within QEMU have done. > > And can use g_strdup_printf() instead of strncat(), which may be more > easier un

Re: [PATCH v2 02/15] arm/arm64: KVM: pass down user space provided GIC type into vGIC code

On Thu, Aug 21, 2014 at 02:06:43PM +0100, Andre Przywara wrote: > With the introduction of a second emulated GIC model we need to let > userspace specify the GIC model to use for each VM. Pass the > userspace provided value down into the vGIC code to differentiate > later. > > Signed-off-by: Andre

Re: [PATCH v2 01/15] arm/arm64: KVM: rework MPIDR assignment and add accessors

On Thu, Aug 21, 2014 at 02:06:42PM +0100, Andre Przywara wrote: > The virtual MPIDR registers (containing topology information) for the > guest are currently mapped linearily to the vcpu_id. Improve this > mapping for arm64 by using three levels to not artificially limit the > number of vCPUs. Also

Re: [PATCH v2 04/15] arm/arm64: KVM: wrap 64 bit MMIO accesses with two 32 bit ones

On Thu, Aug 21, 2014 at 02:06:45PM +0100, Andre Przywara wrote: > Some GICv3 registers can and will be accessed as 64 bit registers. > Currently the register handling code can only deal with 32 bit > accesses, so we do two consecutive calls to cover this. > > Signed-off-by: Andre Przywara > --- >

Re: [PATCH v2 03/15] arm/arm64: KVM: refactor vgic_handle_mmio() function

On Thu, Aug 21, 2014 at 02:06:44PM +0100, Andre Przywara wrote: > Currently we only need to deal with one MMIO region for the GIC > emulation, but we soon need to extend this. Refactor the existing > code to allow easier addition of different ranges without code > duplication. > > Signed-off-by: A

Re: [PATCH v2 05/15] arm/arm64: KVM: introduce per-VM ops

On Thu, Aug 21, 2014 at 02:06:46PM +0100, Andre Przywara wrote: > Currently we only have one virtual GIC model supported, so all guests > use the same emulation code. With the addition of another model we > end up with different guests using potentially different vGIC models, > so we have to split

Re: [PATCH v2 06/15] arm/arm64: KVM: make the maximum number of vCPUs a per-VM value

On Thu, Aug 21, 2014 at 02:06:47PM +0100, Andre Przywara wrote: > Currently the maximum number of vCPUs supported is a global value > limited by the used GIC model. GICv3 will lift this limit, but we > still need to observe it for guests using GICv2. > So the maximum number of vCPUs is per-VM value

Re: [PATCH v2 07/15] arm/arm64: KVM: make the value of ICC_SRE_EL1 a per-VM variable

On Thu, Aug 21, 2014 at 02:06:48PM +0100, Andre Przywara wrote: > ICC_SRE_EL1 is a system register allowing msr/mrs accesses to the > GIC CPU interface for EL1 (guests). Currently we force it to 0, but > for proper GICv3 support we have to allow guests to use it (depending > on their selected virtu

Re: Nested VMX guest tsc_deadline OOPS

On Tue, Oct 14, 2014 at 3:46 AM, Bandan Das wrote: > Andy Lutomirski writes: > >> I don't know what's going on here, but a nested VMX boot using -cpu >> host on SNB on L0 and L1 fails with the OOPS below. I kind of suspect >> that there's both a KVM bug and an APIC driver bug here. > > What kern

Re: reduce networking latency

2014-09-29 5:04 GMT-04:00 Michael S. Tsirkin : > On Wed, Sep 24, 2014 at 02:40:53PM -0400, David Xu wrote: >> Hi Michael, >> >> I found this interesting project from KVM TODO website: >> >> allow handling short packets from softirq or VCPU context >> Plan: >>We are going through the scheduler

Re: [RFC PATCH] arm/arm64: KVM: Fix BE accesses to GICv2 EISR and ELRSR regs

On 14 October 2014 08:21, Victor Kamensky wrote: > On 14 October 2014 02:47, Marc Zyngier wrote: >> On Sun, Sep 28 2014 at 03:04:26 PM, Christoffer Dall >> wrote: >>> The EIRSR and ELRSR registers are 32-bit registers on GICv2, and we >>> store these as an array of two such registers on the vgi