Re: Problems while booting a linux system on fast models based CortexA15

On 18 May 2013 03:26, Mai Daftedar wrote: > > I still have no luck in bringing up the host on fast models. > There is something I'm definitely missing out : > > Theses are my suggested potential errors: > When I execute the following command as mentioned in the pdf > mkfs.ext3 ./disk.img > > The f

[PATCH v3 0/4] KVM/MIPS32: Fixes for Linux 3.10

The following patch set fixes a few issues with KVM/MIPS32 in Linux 3.10. Changes from v2: - Drop KVM-MIPS32-Fix-up-KVM-breakage-caused-by-d532f3d2671 as the offending commit has been reverted and will be submitted upstream via the linux-mips tree. - Integrate with the new 64 bit compatible KV

[PATCH 1/4] KVM/MIPS32: Move include/asm/kvm.h => include/uapi/asm/kvm.h since it is a user visible API.

Signed-off-by: Sanjay Lal --- arch/mips/include/asm/kvm.h | 55 arch/mips/include/uapi/asm/kvm.h | 55 2 files changed, 55 insertions(+), 55 deletions(-) delete mode 100644 arch/mips/include/asm/kvm.h create

[PATCH 2/4] KVM/MIPS32: Wrap calls to gfn_to_pfn() with srcu_read_lock/unlock()

- As suggested by Gleb, wrap calls to gfn_to_pfn() with srcu_read_lock/unlock(). Memory slots should be acccessed from a SRCU read section. - kvm_mips_map_page() now returns an error code to it's callers, instead of calling panic() if it cannot find a mapping for a particular gfn. Signed-off-b

[PATCH 3/4] KVM/MIPS32: Export min_low_pfn.

The KVM module uses the standard MIPS cache management routines, which use min_low_pfn. This creates and indirect dependency, requiring min_low_pfn to be exported. Signed-off-by: Sanjay Lal --- arch/mips/kernel/mips_ksyms.c | 6 ++ arch/mips/kvm/kvm_tlb.c | 1 - 2 files changed, 6 ins

[PATCH 4/4] KVM/MIPS32: Bring in patch from David Daney with new 64 bit compatible ABI.

From: David Daney There are several parts to this: o All registers are 64-bits wide, 32-bit guests use the least significant portion of the register storage fields. o FPU register formats are defined. o CP0 Registers are manipulated via the KVM_GET_MSRS/KVM_SET_MSRS mechanism. The vcpu_io

Re: Bug#707257: linux-image-3.8-1-686-pae: KVM crashes with "entry failed, hardware error 0x80000021"

Dear KVM maintainers, it appears that there is a gap in x86 emulation, at least on a 32-bit host. Stefan found this when running GRML, a live distribution which can be downloaded from: . His original reported is at .

[PATCH v3 01/13] nEPT: Support LOAD_IA32_EFER entry/exit controls for L1

From: Nadav Har'El Recent KVM, since http://kerneltrap.org/mailarchive/linux-kvm/2010/5/2/6261577 switch the EFER MSR when EPT is used and the host and guest have different NX bits. So if we add support for nested EPT (L1 guest using EPT to run L2) and want to be able to run recent KVM as L1, we

[PATCH v3 02/13] nEPT: Move gpte_access() and prefetch_invalid_gpte() to paging_tmpl.h

From: Nadav Har'El For preparation, we just move gpte_access() and prefetch_invalid_gpte() from mmu.c to paging_tmpl.h. Signed-off-by: Nadav Har'El Signed-off-by: Jun Nakajima Signed-off-by: Xinhao Xu --- arch/x86/kvm/mmu.c | 30 -- arch/x86/kvm/paging_tm

[PATCH v3 04/13] nEPT: Define EPT-specific link_shadow_page()

From: Nadav Har'El Since link_shadow_page() is used by a routine in mmu.c, add an EPT-specific link_shadow_page() in paging_tmp.h, rather than moving it. Signed-off-by: Nadav Har'El Signed-off-by: Jun Nakajima Signed-off-by: Xinhao Xu --- arch/x86/kvm/paging_tmpl.h | 20

[PATCH v3 05/13] nEPT: MMU context for nested EPT

From: Nadav Har'El KVM's existing shadow MMU code already supports nested TDP. To use it, we need to set up a new "MMU context" for nested EPT, and create a few callbacks for it (nested_ept_*()). This context should also use the EPT versions of the page table access functions (defined in the prev

[PATCH v3 03/13] nEPT: Add EPT tables support to paging_tmpl.h

From: Nadav Har'El This is the first patch in a series which adds nested EPT support to KVM's nested VMX. Nested EPT means emulating EPT for an L1 guest so that L1 can use EPT when running a nested guest L2. When L1 uses EPT, it allows the L2 guest to set its own cr3 and take its own page faults

[PATCH v3 07/13] nEPT: Fix wrong test in kvm_set_cr3

From: Nadav Har'El kvm_set_cr3() attempts to check if the new cr3 is a valid guest physical address. The problem is that with nested EPT, cr3 is an *L2* physical address, not an L1 physical address as this test expects. As the comment above this test explains, it isn't necessary, and doesn't cor

[PATCH v3 08/13] nEPT: Some additional comments

From: Nadav Har'El Some additional comments to preexisting code: Explain who (L0 or L1) handles EPT violation and misconfiguration exits. Don't mention "shadow on either EPT or shadow" as the only two options. Signed-off-by: Nadav Har'El Signed-off-by: Jun Nakajima Signed-off-by: Xinhao Xu --

[PATCH v3 06/13] nEPT: Fix cr3 handling in nested exit and entry

From: Nadav Har'El The existing code for handling cr3 and related VMCS fields during nested exit and entry wasn't correct in all cases: If L2 is allowed to control cr3 (and this is indeed the case in nested EPT), during nested exit we must copy the modified cr3 from vmcs02 to vmcs12, and we forg

[PATCH v3 09/13] nEPT: Advertise EPT to L1

From: Nadav Har'El Advertise the support of EPT to the L1 guest, through the appropriate MSR. This is the last patch of the basic Nested EPT feature, so as to allow bisection through this patch series: The guest will not see EPT support until this last patch, and will not attempt to use the half

[PATCH v3 10/13] nEPT: Nested INVEPT

From: Nadav Har'El If we let L1 use EPT, we should probably also support the INVEPT instruction. In our current nested EPT implementation, when L1 changes its EPT table for L2 (i.e., EPT12), L0 modifies the shadow EPT table (EPT02), and in the course of this modification already calls INVEPT. Th

[PATCH v3 11/13] nEPT: Miscelleneous cleanups

From: Nadav Har'El Some trivial code cleanups not really related to nested EPT. Signed-off-by: Nadav Har'El Signed-off-by: Jun Nakajima Signed-off-by: Xinhao Xu Reviewed-by: Paolo Bonzini --- arch/x86/kvm/vmx.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/x

[PATCH v3 12/13] nEPT: Move is_rsvd_bits_set() to paging_tmpl.h

Move is_rsvd_bits_set() to paging_tmpl.h so that it can be used to check reserved bits in EPT page table entries as well. Signed-off-by: Jun Nakajima Signed-off-by: Xinhao Xu --- arch/x86/kvm/mmu.c | 8 arch/x86/kvm/paging_tmpl.h | 12 ++-- 2 files changed, 10 insertio

[PATCH v3 13/13] nEPT: Inject EPT violation/misconfigration

Add code to detect EPT misconfiguration and inject it to L1 VMM. Also, it injects more correct exit qualification upon EPT violation to L1 VMM. Now L1 can correctly go to ept_misconfig handler (instead of wrongly going to fast_page_fault), it will try to handle mmio page fault, if failed, it is a

Re: [PATCH v3 01/13] nEPT: Support LOAD_IA32_EFER entry/exit controls for L1

On Mon, May 13, 2013 at 5:25 AM, Gleb Natapov wrote: > Please use --no-chain-reply-to option to "git send-email" for nicer > email threading and there is something wrong with Signed-off chain for > the patches. The first Signed-off-by: is by Nadav, but you appears to be > the author of the patches

[PATCH 00/18] KVM/MIPS32: Support for the new Virtualization ASE (VZ-ASE)

The following patch set adds support for the recently announced virtualization extensions for the MIPS32 architecture and allows running unmodified kernels in Guest Mode. For more info please refer to : MIPS Document #: MD00846 Volume IV-i: Virtualization Module of the MIPS32 Archi

[PATCH 02/18] Revert "MIPS: Allow ASID size to be determined at boot time."

This reverts commit d532f3d26716a39dfd4b88d687bd344fbe77e390. Conflicts: arch/mips/mm/tlbex.c Signed-off-by: Sanjay Lal --- arch/mips/include/asm/mmu_context.h | 95 ++--- arch/mips/kernel/genex.S| 2 +- arch/mips/kernel/smtc.c |

[PATCH 01/18] Revert "MIPS: microMIPS: Support dynamic ASID sizing."

This reverts commit f6b06d9361a008afb93b97fb3683a6e92d69d0f4. Signed-off-by: Sanjay Lal --- arch/mips/mm/tlbex.c | 34 ++ 1 file changed, 2 insertions(+), 32 deletions(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 4d46d37..2ad41e9 100644 --- a

[PATCH 05/18] KVM/MIPS32-VZ: VZ-ASE assembler wrapper functions to set GuestIDs

Signed-off-by: Sanjay Lal --- arch/mips/kvm/kvm_vz_locore.S | 74 +++ 1 file changed, 74 insertions(+) create mode 100644 arch/mips/kvm/kvm_vz_locore.S diff --git a/arch/mips/kvm/kvm_vz_locore.S b/arch/mips/kvm/kvm_vz_locore.S new file mode 100644 index

[PATCH 03/18] KVM/MIPS32: Export min_low_pfn.

The KVM module uses the standard MIPS cache management routines, which use min_low_pfn. This creates and indirect dependency, requiring min_low_pfn to be exported. Signed-off-by: Sanjay Lal --- arch/mips/kernel/mips_ksyms.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/ker

[PATCH 04/18] KVM/MIPS32-VZ: MIPS VZ-ASE related register defines and helper macros.

Signed-off-by: Sanjay Lal --- arch/mips/include/asm/mipsvzregs.h | 494 + 1 file changed, 494 insertions(+) create mode 100644 arch/mips/include/asm/mipsvzregs.h diff --git a/arch/mips/include/asm/mipsvzregs.h b/arch/mips/include/asm/mipsvzregs.h new file m

[PATCH 07/18] KVM/MIPS32: VZ-ASE related CPU feature flags and options.

- GuestIDs and Virtual IRQs are optional - New TLBINV instruction is also optional Signed-off-by: Sanjay Lal --- arch/mips/include/asm/cpu-features.h | 36 arch/mips/include/asm/cpu-info.h | 21 + arch/mips/include/asm/cpu.h |

[PATCH 13/18] KVM/MIPS32-VZ: Top level handler for Guest faults

- Add VZ specific VM Exit reasons to the traces. - Add top level handler for Guest Exit exceptions. Signed-off-by: Sanjay Lal --- arch/mips/kvm/kvm_mips.c | 73 +++- 1 file changed, 53 insertions(+), 20 deletions(-) diff --git a/arch/mips/kvm/kvm_mips

[PATCH 06/18] KVM/MIPS32-VZ: VZ-ASE related callbacks to handle guest exceptions that trap to the Root context.

The VZ-ASE provices the Guest with its own COP0 context, so the types of exceptions that will trap to the root a lot fewer than in the trap and emulate case. - Root level TLB miss handlers that map GPAs to RPAs. - Guest Exits Signed-off-by: Sanjay Lal --- arch/mips/kvm/kvm_vz.c | 786 +

[PATCH 08/18] KVM/MIPS32-VZ: Entry point for trampolining to the guest and trap handlers.

- Add support for the MIPS VZ-ASE - Whitespace fixes Signed-off-by: Sanjay Lal --- arch/mips/kvm/kvm_locore.S | 1088 +++- 1 file changed, 573 insertions(+), 515 deletions(-) diff --git a/arch/mips/kvm/kvm_locore.S b/arch/mips/kvm/kvm_locore.S index dca2a

[PATCH 17/18] KVM/MIPS32: Revert to older method for accessing ASID parameters

- Now that commit d532f3d26 has been reverted in the MIPS tree, revert back to the older method of using the ASID_MASK. - Trivial cleanup: s/unsigned long/long Signed-off-by: Sanjay Lal --- arch/mips/kvm/kvm_mips_dyntrans.c | 24 ++-- arch/mips/kvm/kvm_mips_emul.c | 236 ++

[PATCH 09/18] KVM/MIPS32-VZ: Add support for CONFIG_KVM_MIPS_VZ option

- Add config option for KVM/MIPS with VZ support. Signed-off-by: Sanjay Lal --- arch/mips/kvm/Kconfig | 14 +- arch/mips/kvm/Makefile | 14 +- 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/arch/mips/kvm/Kconfig b/arch/mips/kvm/Kconfig index 2c15590..963

[PATCH 10/18] KVM/MIPS32-VZ: Add API for VZ-ASE Capability

- Add API to allow clients (QEMU etc.) to check whether the H/W supports the MIPS VZ-ASE. Signed-off-by: Sanjay Lal --- include/uapi/linux/kvm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index a5c86fc..5889e976 100644 --- a/include/

[PATCH 11/18] KVM/MIPS32-VZ: VZ: Handle Guest TLB faults that are handled in Root context

- Guest physical addresses need to be mapped by the Root TLB. Signed-off-by: Sanjay Lal --- arch/mips/kvm/kvm_tlb.c | 444 +++- 1 file changed, 359 insertions(+), 85 deletions(-) diff --git a/arch/mips/kvm/kvm_tlb.c b/arch/mips/kvm/kvm_tlb.c index 895

[PATCH 12/18] KVM/MIPS32-VZ: VM Exit Stats, add VZ exit reasons.

- Additional VZ related exit reasons, used in the trace logs. Signed-off-by: Sanjay Lal --- arch/mips/kvm/kvm_mips_stats.c | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/mips/kvm/kvm_mips_stats.c b/arch/mips/kvm/kvm_mips_stats.c index 075904b..c0d0c0f

[PATCH 14/18] KVM/MIPS32-VZ: Guest exception batching support.

- In Trap & Emulate the hypervisor maintains exception priority in order to comply with the priorities defined by the architecture. - In VZ mode, we just set all the pending exception bits, and let the processor deliver them to the guest in the expected priority order. Signed-off-by: Sanjay

[PATCH 15/18] KVM/MIPS32: Add dummy trap handler to catch unexpected exceptions and dump out useful info

Signed-off-by: Sanjay Lal --- arch/mips/kvm/kvm_trap_emul.c | 68 --- 1 file changed, 44 insertions(+), 24 deletions(-) diff --git a/arch/mips/kvm/kvm_trap_emul.c b/arch/mips/kvm/kvm_trap_emul.c index 466aeef..19b32a1 100644 --- a/arch/mips/kvm/kvm_trap_e

[PATCH 16/18] KVM/MIPS32-VZ: Add VZ-ASE support to KVM/MIPS data structures.

Signed-off-by: Sanjay Lal --- arch/mips/include/asm/kvm_host.h | 244 ++- 1 file changed, 191 insertions(+), 53 deletions(-) diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h index e68781e..c92e297 100644 --- a/arch/mips/include

[PATCH 18/18] KVM/MIPS32-VZ: Dump out additional info about VZ features as part of /proc/cpuinfo

Signed-off-by: Sanjay Lal --- arch/mips/kernel/proc.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index a3e4614..308e042 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -99,6 +99,17 @@ static int show_cp

Re: [RFC PATCH 1/2] Hyper-H reference counter

On Thu, 2013-05-16 at 16:45 +0200, Paolo Bonzini wrote: > Il 16/05/2013 16:26, Vadim Rozenfeld ha scritto: > > > >>> > > > >>> Yes, I have this check added in the second patch. > > > >>> > > >> Move it here please. > >>> > > OK, will do it. > >> > > >> > Or better, remove all the