On 11/09/14 04:12, Christoffer Dall wrote:
> On Tue, Sep 09, 2014 at 12:02:59PM +0100, Marc Zyngier wrote:
>> [resending, as ARM email server seems to be in some mood]
>>
>> On 09/09/14 11:27, Ard Biesheuvel wrote:
>>> The ISS encoding for an exception from a Data Abort has a WnR
>>> bit[6] that in
On Tue, Sep 09, 2014 at 12:02:59PM +0100, Marc Zyngier wrote:
> [resending, as ARM email server seems to be in some mood]
>
> On 09/09/14 11:27, Ard Biesheuvel wrote:
> > The ISS encoding for an exception from a Data Abort has a WnR
> > bit[6] that indicates whether the Data Abort was caused by a
On 09/09/14 11:27, Ard Biesheuvel wrote:
> The ISS encoding for an exception from a Data Abort has a WnR
> bit[6] that indicates whether the Data Abort was caused by a
> read or a write instruction. While there are several fields
> in the encoding that are only valid if the ISV bit[24] is set,
> Wn
[resending, as ARM email server seems to be in some mood]
On 09/09/14 11:27, Ard Biesheuvel wrote:
> The ISS encoding for an exception from a Data Abort has a WnR
> bit[6] that indicates whether the Data Abort was caused by a
> read or a write instruction. While there are several fields
> in the e
The ISS encoding for an exception from a Data Abort has a WnR
bit[6] that indicates whether the Data Abort was caused by a
read or a write instruction. While there are several fields
in the encoding that are only valid if the ISV bit[24] is set,
WnR is not one of them, so we can read it uncondition
