Christoffer Dall writes:
> On Tue, Nov 25, 2014 at 04:10:02PM +, Alex Bennée wrote:
>> This adds support for SW breakpoints inserted by userspace.
>>
>> First we need to trap all BKPT exceptions in the hypervisor (ELS). This
>> in controlled through the MDCR_EL2 register. I've added a new f
On Tue, Nov 25, 2014 at 04:10:02PM +, Alex Bennée wrote:
> This adds support for SW breakpoints inserted by userspace.
>
> First we need to trap all BKPT exceptions in the hypervisor (ELS). This
> in controlled through the MDCR_EL2 register. I've added a new field to
this is ?
> the vcpu str
On Wed, Nov 26, 2014 at 05:07:20PM +0100, Andrew Jones wrote:
> On Tue, Nov 25, 2014 at 04:10:02PM +, Alex Bennée wrote:
> > This adds support for SW breakpoints inserted by userspace.
> >
> > First we need to trap all BKPT exceptions in the hypervisor (ELS). This
> > in controlled through the
On 26 November 2014 at 16:07, Andrew Jones wrote:
> There appears to be a typo in the ARM ARM. Subsection "Software
> Breakpoint Instruction exception" of D1.10.4 says BRK (ESR_EL2_EC_BRK64)
> is 0x39, but the table above that has it correctly as 0x3c.
Thanks for pointing out this typo -- I've re
On Tue, Nov 25, 2014 at 04:10:02PM +, Alex Bennée wrote:
> This adds support for SW breakpoints inserted by userspace.
>
> First we need to trap all BKPT exceptions in the hypervisor (ELS). This
> in controlled through the MDCR_EL2 register. I've added a new field to
> the vcpu structure to ho
This adds support for SW breakpoints inserted by userspace.
First we need to trap all BKPT exceptions in the hypervisor (ELS). This
in controlled through the MDCR_EL2 register. I've added a new field to
the vcpu structure to hold this value. There should be scope to
rationlise this with the VCPU_D
