On Thu, Jun 25, 2015 at 1:07 AM, John Nielsen wrote:
> Interesting. Using the same PC-BSD image I am able to reproduce on a server
> running slightly older software but I can not reproduce running bleeding
> edge. I verified enable_apicv=Y on both. In both cases I ran
> qemu-kvm -drive if=virtio
On Wed, Mar 4, 2015 at 11:58 PM, Bandan Das wrote:
> Hi Wincy,
>
> Wincy Van writes:
>
>> In commit 3af18d9c5fe9 ("KVM: nVMX: Prepare for using hardware MSR bitmap"),
>> we are setting MSR_BITMAP in prepare_vmcs02 if we should use hardware. This
>> is not
_bitmap if vcpu is
in guest mode.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 11 +++
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index f7b20b4..10a481b 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -2168,
On Wed, Mar 4, 2015 at 12:04 PM, Bandan Das wrote:
> Wincy Van writes:
>
>> On Wed, Mar 4, 2015 at 1:39 AM, Bandan Das wrote:
>>> Wincy Van writes:
>>>
>>>> In commit 3af18d9c5fe9 ("KVM: nVMX: Prepare for using hardware MSR
>>>> bitma
On Wed, Mar 4, 2015 at 1:39 AM, Bandan Das wrote:
> Wincy Van writes:
>
>> In commit 3af18d9c5fe9 ("KVM: nVMX: Prepare for using hardware MSR bitmap"),
>> we are setting MSR_BITMAP in prepare_vmcs02 if we should use hardware. This
>> is not enough since the f
_bitmap if vcpu is
in guest mode.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index f7b20b4..f6e3457 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -2168,7 +2168,10
On Sun, Feb 15, 2015 at 2:27 PM, Yong Wang wrote:
>
> Wincy, our QA found regressions with this patch that 64bit L2 linux guest
> fails to boot up when running nested kvm on kvm.
>
> Environment:
>
> Host OS (ia32/ia32e/IA64):ia32e
> Guest OS (ia32/ia32e/IA64):ia32e
> Guest OS Type (L
On Sun, Feb 15, 2015 at 2:27 PM, Yong Wang wrote:
> On Tue, Feb 03, 2015 at 11:58:17PM +0800, Wincy Van wrote:
>> If vcpu has a interrupt in vmx non-root mode, we will
>> kick that vcpu to inject interrupt timely. With posted
>> interrupt processing, the kick intr is not need
On Wed, Feb 4, 2015 at 12:15 AM, Paolo Bonzini wrote:
>
>
> On 03/02/2015 16:46, Wincy Van wrote:
>> v1 ---> v2:
>> Use spin lock to ensure vmcs12 is safe when doing nested
>> posted interrupt delivery.
>>
>> v2 ---> v3:
>> 1. Add a n
interrupt, the posted intr bit
in the nested_vmx_pinbased_ctls_high will be cleared.
Since there would be different settings about in-kernel
irqchip between VMs, different nested control MSRs
are needed.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 215
duces nested_vmx_merge_msr_bitmap for future use.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 77 ---
1 files changed, 66 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 81152a0..4108676 100644
--- a/arc
use L0's POSTED_INTR_NV to avoid unexpected
interrupt if L1's vector is different with L0's. If vcpu
is in hardware's non-root mode, we use a physical ipi to
deliver posted interrupts, otherwise we will accomplish
that posted interrupt in nested vm-entry manually.
Sign
plish nested posted interrupts manually if
they are not recognized by hardware.
Wincy Van (6):
KVM: nVMX: Use hardware MSR bitmap
KVM: nVMX: Enable nested virtualize x2apic mode
KVM: nVMX: Make nested control MSRs per-cpu
KVM: nVMX: Enable nested apic register virtualization
KVM:
We can reduce apic register virtualization cost with this feature,
it is also a requirement for virtual interrupt delivery and posted
interrupt processing.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 39 +++
1 files changed, 35 insertions(+), 4
With virtual interrupt delivery, the hardware prevent KVM from
the low efficiency interrupt inject way. In nested vmx, it is
a important feature, we can reduce much more nested-vmexit,
especially in high throughput scenes.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 67
When L2 is using x2apic, we can use virtualize x2apic mode to
gain higher performance, especially in apicv case.
This patch also introduces nested_vmx_check_apicv_controls
for the nested apicv patches.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 114
On Tue, Feb 3, 2015 at 10:02 PM, Paolo Bonzini wrote:
>
>
> On 03/02/2015 10:17, Wincy Van wrote:
>> +static int vmx_accomp_nested_posted_interrupt(struct kvm_vcpu *vcpu)
>
> Replace accomp with complete.
Will do.
>
>> +{
>> + struct vcpu_vmx *vmx =
On Tue, Feb 3, 2015 at 9:57 PM, Paolo Bonzini wrote:
>
>
> On 03/02/2015 10:11, Wincy Van wrote:
>> @@ -8468,6 +8484,38 @@ static void vmx_start_preemption_timer(struct
>> kvm_vcpu *vcpu)
>> ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
>&
use L0's POSTED_INTR_NV to avoid unexpected
interrupt if L1's vector is different with L0's. If vcpu
is in hardware's non-root mode, we use a physical ipi to
deliver posted interrupts, otherwise we will accomplish
that posted interrupt in nested vm-entry manually.
Sign
With virtual interrupt delivery, the hardware prevent KVM from
the low efficiency interrupt inject way. In nested vmx, it is
a important feature, we can reduce much more nested-vmexit,
especially in high throughput scenes.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 67
We can reduce apic register virtualization cost with this feature,
it is also a requirement for virtual interrupt delivery and posted
interrupt processing.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 39 +++
1 files changed, 35 insertions(+), 4
interrupt, the posted intr bit
in the nested_vmx_pinbased_ctls_high will be cleared.
Since there would be different settings about in-kernel
irqchip between VMs, different nested control MSRs
are needed.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 215
When L2 is using x2apic, we can use virtualize x2apic mode to
gain higher performance, especially in apicv case.
This patch also introduces nested_vmx_check_apicv_controls
for the nested apicv patches.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 114
duces nested_vmx_merge_msr_bitmap for future use.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 77 ---
1 files changed, 66 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 81152a0..4108676 100644
--- a/arc
plish nested posted interrupts manually if
they are not recognized by hardware.
Wincy Van (6):
KVM: nVMX: Use hardware MSR bitmap
KVM: nVMX: Enable nested virtualize x2apic mode
KVM: nVMX: Make nested control MSRs per-cpu
KVM: nVMX: Enable nested apic register virtualization
KVM:
On Tue, Feb 3, 2015 at 9:21 AM, Zhang, Yang Z wrote:
> Paolo Bonzini wrote on 2015-02-03:
>>
>>
>> On 02/02/2015 16:33, Wincy Van wrote:
>>> static void vmx_accomp_nested_posted_intr(struct kvm_vcpu *vcpu) {
>>> struct vcpu_vmx *vmx = to_vmx(vcpu);
On Mon, Feb 2, 2015 at 7:03 PM, Paolo Bonzini wrote:
>
>
> On 28/01/2015 17:02, Wincy Van wrote:
>> +static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
>> + int vector)
>> +{
>&g
On Thu, Jan 29, 2015 at 11:17 AM, Zhang, Yang Z wrote:
> Wincy Van wrote on 2015-01-28:
>> v1 ---> v2:
>> Use spin lock to ensure vmcs12 is safe when doing nested
>> posted interrupt delivery.
>> v2 ---> v3:
>> 1. Add a new field in nested_vmx to avoid
duces nested_vmx_merge_msr_bitmap for future use.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 77 ---
1 files changed, 66 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index c987374..787f886 100644
--- a/arc
On Thu, Jan 29, 2015 at 10:54 AM, Zhang, Yang Z wrote:
>> -8646,7 +8750,8 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu,
>> struct vmcs12 *vmcs12)
>> else
>> vmcs_write64(APIC_ACCESS_ADDR,
>>
>> page_to_phys(vmx->nested.apic_access_page
duces nested_vmx_merge_msr_bitmap for future use.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 77 ---
1 files changed, 66 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index c987374..787f886 100644
--- a/arc
On Wed, Jan 28, 2015 at 4:05 PM, Zhang, Yang Z wrote:
>> @@ -8344,7 +8394,68 @@ static int
>> nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, static
>> inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
>>struct vmcs12
>> *vm
We can reduce apic register virtualization cost with this feature,
it is also a requirement for virtual interrupt delivery and posted
interrupt processing.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 36
1 files changed, 32 insertions(+), 4 deletions
Sorry, please ignore this mail, the subject is wrong : (
On Wed, Jan 28, 2015 at 11:50 PM, Wincy Van wrote:
> Currently, if L1 enables MSR_BITMAP, we will emulate this feature,
> all of L2's msr access is intercepted by L0. Since many features
> like virtualize x2apic mode has
ualize x2apic
mode.
v3 ---> v4:
1. Optimize nested msr bitmap merging.
2. Allocate nested msr bitmap only when nested == 1.
3. Inline the nested vmx control checking functions.
Wincy Van (6):
KVM: nVMX: Use hardware MSR bitmap
KVM: nVMX: Enable nested virtualize x2apic mode
With virtual interrupt delivery, the hardware prevent KVM from
the low efficiency interrupt inject way. In nested vmx, it is
a important feature, we can reduce much more nested-vmexit,
especially in high throughput scenes.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 68
On Wed, Jan 28, 2015 at 8:33 PM, Zhang, Yang Z wrote:
>>>
>>> You are right, but this is not fit for all the cases, we should
>>> custom the nested_msr_bitmap.
>>> e.g. Currently L0 wants to intercept some of the x2apic msrs' reading:
>>> if (enable_apicv) {
>>> for (msr
On Wed, Jan 28, 2015 at 3:31 PM, Paolo Bonzini wrote:
>>> >
>>> > No need for this function and nested_cpu_has_virt_x2apic_mode. Just
>>> > inline them in their caller(s). Same for other cases throughout the
>>> > series.
>>> >
>> Do you mean that we should also inline the same functions in the
On Wed, Jan 28, 2015 at 4:00 PM, Zhang, Yang Z wrote:
>> @@ -5812,13 +5813,18 @@ static __init int hardware_setup(void)
>> (unsigned long
>> *)__get_free_page(GFP_KERNEL);
>> if (!vmx_msr_bitmap_longmode_x2apic)
>> goto out4;
>> +
>> +
interrupt, the posted intr bit
in the nested_vmx_pinbased_ctls_high will be cleared.
Since there would be different settings about in-kernel
irqchip between VMs, different nested control MSRs
are needed.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 215
When L2 is using x2apic, we can use virtualize x2apic mode to
gain higher performance, especially in apicv case.
This patch also introduces nested_vmx_check_apicv_controls
for the nested apicv patches.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 114
mode.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 84 ++--
1 files changed, 81 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index ab131f3..85a163c 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vm
On Wed, Jan 28, 2015 at 11:52 PM, Wincy Van wrote:
> Sorry, please ignore this mail, the subject is wrong : (
>
I was confused by gmail's conversation view, gmail put this patch in
the v3's conversation.
please ignore this.
Thanks,
Wincy
> On Wed, Jan 28, 2015 at 11:50 P
On Wed, Jan 28, 2015 at 9:06 PM, Zhang, Yang Z wrote:
__clear_bit(msr, msr_bitmap_nested + 0x000 / f);
>>>
>>>
>>> Anyway, this is not necessary for your current patch. We can consider
>>> it later if there really have other features will use it.
>>>
>>
>> Yep, I know what you mean no
On Wed, Jan 28, 2015 at 7:52 PM, Zhang, Yang Z wrote:
>>>
>>
>> If L0 wants to intercept a msr, we should set
>> vmx_msr_bitmap_legacy(_x2apic) and vmx_msr_bitmap_longmode(_x2apic),
>> and that bitmaps should only be loaded in non-nested entry.
>> Currently we only clear the corresponding bits if
On Wed, Jan 28, 2015 at 7:25 PM, Zhang, Yang Z wrote:
> Wincy Van wrote on 2015-01-28:
>> On Wed, Jan 28, 2015 at 4:05 PM, Zhang, Yang Z
>> wrote:
>>>> @@ -8344,7 +8394,68 @@ static int
>>>> nested_vmx_check_msr_bitmap_controls(struct k
On Wed, Jan 28, 2015 at 6:06 AM, Paolo Bonzini wrote:
>
>
> On 24/01/2015 11:18, Wincy Van wrote:
>> v2 ---> v3:
>> 1. Add a new field in nested_vmx to avoid the spin lock in v2.
>> 2. Drop send eoi to L1 when doing nested interrupt delivery.
>> 3. Use
On Wed, Jan 28, 2015 at 5:39 AM, Paolo Bonzini wrote:
>
>
> On 24/01/2015 11:21, Wincy Van wrote:
>> +static void nested_vmx_disable_intercept_for_msr(unsigned long
>> *msr_bitmap_l1,
>> + unsigned
On Wed, Jan 28, 2015 at 5:37 AM, Paolo Bonzini wrote:
>
>
> On 24/01/2015 11:21, Wincy Van wrote:
>> + memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
>
> Most bytes are always 0xff. It's better to initialize it to 0xff once,
> and set the bit here if !ne
On Wed, Jan 28, 2015 at 5:55 AM, Paolo Bonzini wrote:
>
>
> On 24/01/2015 11:24, Wincy Van wrote:
>> if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
>> !nested_cpu_has_apic_reg_virt(vmcs12) &&
>> - !nested_cpu_has_vid(
mode.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 90 ++--
1 files changed, 87 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 5d8500c..4e4b64e 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vm
With virtual interrupt delivery, the hardware prevent KVM from
the low efficiency interrupt inject way. In nested vmx, it is
a important feature, we can reduce much more nested-vmexit,
especially in high throughput scenes.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 63
We can reduce apic register virtualization cost with this feature,
it is also a requirement for virtual interrupt delivery and posted
interrupt processing.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 24
1 files changed, 20 insertions(+), 4 deletions(-)
diff
interrupt, the posted intr bit
in the nested_vmx_pinbased_ctls_high will be cleared.
Since there would be different settings about in-kernel
irqchip between VMs, different nested control MSRs
are needed.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 215
When L2 is using x2apic, we can use virtualize x2apic mode to
gain higher performance, especially in apicv case.
This patch also introduces nested_vmx_check_apicv_controls
for the nested apicv patches.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 121
duces nested_vmx_merge_msr_bitmap for future use.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 71 +++
1 files changed, 60 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index c987374..36d0724 100644
--- a/arc
ualize x2apic
mode.
Wincy Van (6):
KVM: nVMX: Use hardware MSR bitmap
KVM: nVMX: Enable nested virtualize x2apic mode.
KVM: nVMX: Make nested control MSRs per-cpu.
KVM: nVMX: Enable nested apic register virtualization.
KVM: nVMX: Enable nested virtual interrupt delivery.
KVM: nVMX:
On Wed, Jan 21, 2015 at 4:49 PM, Zhang, Yang Z wrote:
+ if (vector == vmcs12->posted_intr_nv && +
nested_cpu_has_posted_intr(vmcs12)) { + if (vcpu->mode
== IN_GUEST_MODE) + apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), +
POSTED_INTR_
On Wed, Jan 21, 2015 at 4:35 PM, Zhang, Yang Z wrote:
> Wincy Van wrote on 2015-01-16:
>> When L2 is using x2apic, we can use virtualize x2apic mode to gain higher
>> performance.
>>
>> This patch also introduces nested_vmx_check_apicv_controls for the nested
>> a
On Wed, Jan 21, 2015 at 4:18 PM, Zhang, Yang Z wrote:
> Wincy Van wrote on 2015-01-16:
>> To enable nested apicv support, we need per-cpu vmx control MSRs:
>> 1. If in-kernel irqchip is enabled, we can enable nested
>> posted interrupt, we should set p
On Wed, Jan 21, 2015 at 4:07 PM, Zhang, Yang Z wrote:
>> + if (vector == vmcs12->posted_intr_nv &&
>> + nested_cpu_has_posted_intr(vmcs12)) {
>> + if (vcpu->mode == IN_GUEST_MODE)
>> + apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
>> +
On Tue, Jan 20, 2015 at 5:54 PM, Paolo Bonzini wrote:
>
>
> On 20/01/2015 09:48, Wincy Van wrote:
>> +static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
>> + int vector)
>> +{
>> + int r = 0;
mode.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 136 ++--
1 files changed, 132 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index ea56e9f..cda9133 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vm
On Tue, Jan 20, 2015 at 3:34 PM, Paolo Bonzini wrote:
>> Hence, we can disable local interrupts while delivering nested posted
>> interrupts to make sure
>> we are faster than the destination vcpu. This is a bit tricky but it
>> an avoid that race. I think we
>> do not need to add a spin lock here
Hi, Yang,
Could you please have a look at this patch set?
Your comment is very appreciated!
Thanks,
Wincy
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On Mon, Jan 19, 2015 at 7:43 PM, Paolo Bonzini wrote:
> Hi Wincy,
>
> there is only one thing that I don't understand in this patchset, and it is:
>
> On 16/01/2015 06:59, Wincy Van wrote:
>> + /*
>> +* if vcpu is in L2, we are fast enough to complete
mode.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 131 ++--
1 files changed, 127 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index ea56e9f..5aeef79 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vm
With virtual interrupt delivery, the hardware prevent KVM from
the low efficiency interrupt inject way. In nested vmx, it is
a important feature, we can reduce much more nested-vmexit,
especially in high throughput scenes.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 49
We can reduce apic register virtualization cost with this feature,
it is also a requirement for virtual interrupt delivery and posted
interrupt processing.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 12 ++--
1 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch
When L2 is using x2apic, we can use virtualize x2apic mode to
gain higher performance.
This patch also introduces nested_vmx_check_apicv_controls
for the nested apicv patches.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 49 -
1 files
interrupt, the posted intr bit
in the nested_vmx_pinbased_ctls_high will be cleared.
Since there would be different settings about in-kernel
irqchip between VMs, different nested control MSRs
are needed.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 215
vcpus, 16GB memory.
1. Run iperf -s -w 64k in L1,
iperf -c 10.1.0.2 -p 5001 -i 1 -t 30 -P 8 -w 64k in L2
originalnested apicv
6.58 Gbits/s 14.2 Gbits/s
Improvement: 115.8%
Wincy Van (5):
KVM: nVMX: Make nested control MSRs per-cpu.
KVM
Ping..
Hi, Paolo, could you please have a look at this patch ?
Thanks,
Wincy
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2014-12-24 23:29 GMT+08:00 Jan Kiszka :
> On 2014-12-24 04:14, Wincy Van wrote:
>> This patch fixes the bug discussed in
>> https://www.mail-archive.com/kvm@vger.kernel.org/msg109813.html
>>
>> This patch uses a new field named irr_delivered to record the
>>
commit 0bc830b05c667218d703f2026ec866c49df974fc
("KVM: ioapic: clear IRR for edge-triggered interrupts at delivery")
while avoids the bug of Windows guests.
Signed-off-by: Wincy Van
---
arch/x86/kvm/ioapic.c |7 ++-
arch/x86/kvm/ioapic.h |1 +
2 files changed, 7 insert
2014-12-19 17:50 GMT+08:00 Paolo Bonzini :
>
>
> On 19/12/2014 04:58, Wincy Van wrote:
>> 2014-12-17 18:46 GMT+08:00 Paolo Bonzini :
>>>
>>>
>>> On 17/12/2014 04:46, Wincy Van wrote:
>>>> Hi, all:
>>>>
>>>> The patchse
2014-12-17 18:46 GMT+08:00 Paolo Bonzini :
>
>
> On 17/12/2014 04:46, Wincy Van wrote:
>> Hi, all:
>>
>> The patchset (https://lkml.org/lkml/2014/3/18/309) fixed migration of
>> Windows guests, but commit 0bc830b05c667218d703f2026ec866c49df974fc
>> (KV
Hi, all:
The patchset (https://lkml.org/lkml/2014/3/18/309) fixed migration of
Windows guests, but commit 0bc830b05c667218d703f2026ec866c49df974fc
(KVM: ioapic: clear IRR for edge-triggered interrupts at delivery)
introduced a bug (see
https://www.mail-archive.com/kvm@vger.kernel.org/msg109813.htm
-exit
MSR load area, and load them via kvm_set_msr.
Signed-off-by: Wincy Van
---
arch/x86/include/uapi/asm/vmx.h | 5 +++
arch/x86/kvm/vmx.c | 68 +
arch/x86/kvm/x86.c | 1 +
virt/kvm/kvm_main.c | 1 +
4 files changed
2014-12-10 17:01 GMT+08:00 Wanpeng Li :
> Hi all,
> On Wed, Dec 10, 2014 at 08:07:45AM -0100, Eugene Korenevsky wrote:
>>> Hi, Eugene, is it okay to split my part up?
>>
>>I think the patch is atomic. No ideas how this patch could be split
>>without breaking its integrity.
>>You are a co-author of
2014-12-10 5:12 GMT+08:00 Eugene Korenevsky :
>> I have added Jan and Wincy to the CC list since they reviewed your earlier
>> proposal.
>> I think it would be better to split this up as I mentioned earlier, however,
>> if the other reviewers and the maintainer don't have objections, I am ok :)
>
other patch that was posted for this functionality
> > by Wincy Van ?
> >
> > https://lkml.org/lkml/2014/11/21/749
This patch is misformated, I have already sent out a corrected one:
https://lkml.org/lkml/2014/11/22/61
>
>
> It's good to see more momentum here, but,
MSR load area, and load them via kvm_set_msr.
VirtualBox will work fine with this patch.
Signed-off-by: Wincy Van
---
arch/x86/include/uapi/asm/vmx.h |5 ++
arch/x86/kvm/vmx.c | 123 --
arch/x86/kvm/x86.c |1 +
virt/kvm
MSR load area, and load them via kvm_set_msr.
VirtualBox will work fine with this patch.
Signed-off-by: Wincy Van
diff --git a/arch/x86/include/uapi/asm/vmx.h b/arch/x86/include/uapi/asm/vmx.h
index 990a2fe..986af3f 100644
--- a/arch/x86/include/uapi/asm/vmx.h
+++ b/arch/x86/include/uapi/asm
ll lost response. Please use vnc to run Ubuntu.
5. If your cpu do not support ept, please give the guest only 1vcpu if the
guest is 64 bit. Or the guest will corrupt.
Regards,
Wincy
-邮件原件-
发件人: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] 代表 Andreas
F?rber
发送时间: 2
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