On 2016/1/7 19:03, Marc Zyngier wrote:
> On 22/12/15 08:08, Shannon Zhao wrote:
>> > From: Shannon Zhao
>> >
>> > These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
>> > which is mapped to PMEVTYPERn or PMCCFILTR.
>> >
>>
On 2015/12/22 16:08, Shannon Zhao wrote:
> From: Shannon Zhao
>
> These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
> which is mapped to PMEVTYPERn or PMCCFILTR.
>
> The access handler translates all aarch32 register offsets to aarch64
> ones and u
On 2016/1/7 18:43, Marc Zyngier wrote:
> On 22/12/15 08:07, Shannon Zhao wrote:
>> > From: Shannon Zhao
>> >
>> > Add reset handler which gets host value of PMCR_EL0 and make writable
>> > bits architecturally UNKNOWN except PMCR.E which is ze
On 2016/1/7 18:14, Marc Zyngier wrote:
> On 22/12/15 08:08, Shannon Zhao wrote:
>> > From: Shannon Zhao
>> >
>> > This register resets as unknown in 64bit mode while it resets as zero
>> > in 32bit mode. Here we choose to reset it as zero for consisten
On 2016/1/7 19:03, Marc Zyngier wrote:
> On 22/12/15 08:08, Shannon Zhao wrote:
>> > From: Shannon Zhao
>> >
>> > These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
>> > which is mapped to PMEVTYPERn or PMCCFILTR.
>> >
>>
ading to a mildly confused
> guest.
>
> Solve this by snapshoting PC before the access is performed,
> and checking if it has moved or not before incrementing it.
>
> Reported-by: Shannon Zhao
> Signed-off-by: Marc Zyngier
Reviewed-by: Shannon Zhao
> ---
> arch/ar
ading to a mildly confused
> guest.
>
> Solve this by snapshoting PC before the access is performed,
> and checking if it has moved or not before incrementing it.
>
Thanks a lot. This solves the problem of guest PMU failing to inject EL1
fault to guest.
Tested-by: Shannon Zhao
Reviewed-
From: Shannon Zhao
These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which
is mapped to PMEVCNTRn.
The access handler translates all aarch32 register offsets to aarch64
ones and uses vcpu_sys_reg() to access their values to avoid taking care
of big endian.
When reading these
From: Shannon Zhao
Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMOVSSET or PMOVSCLR register.
When writing non-zero value to PMOVSSET, the counter and its interrupt
is enabled, kick this vcpu to sync PMU
From: Shannon Zhao
These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
which is mapped to PMEVTYPERn or PMCCFILTR.
The access handler translates all aarch32 register offsets to aarch64
ones and uses vcpu_sys_reg() to access their values to avoid taking care
of big endian.
When
From: Shannon Zhao
This register resets as unknown in 64bit mode while it resets as zero
in 32bit mode. Here we choose to reset it as zero for consistency.
PMUSERENR_EL0 holds some bits which decide whether PMU registers can be
accessed from EL0. Add some check helpers to handle the access from
From: Shannon Zhao
Add reset handler which gets host value of PMCR_EL0 and make writable
bits architecturally UNKNOWN except PMCR.E which is zero. Add an access
handler for PMCR.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 39 +--
1 file
From: Shannon Zhao
This helper forward the trap caused by MRS/MSR for arch64 and MCR/MRC,
MCRR/MRRC for arch32 CP15 to guest EL1.
Signed-off-by: Shannon Zhao
---
arch/arm64/include/asm/kvm_emulate.h | 1 +
arch/arm64/kvm/inject_fault.c| 52 +++-
2
From: Shannon Zhao
Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMCNTENSET or PMCNTENCLR register.
When writing to PMCNTENSET, call perf_event_enable to enable the perf
event. When writing to PMCNTENCLR
From: Shannon Zhao
Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMINTENSET or PMINTENCLR register.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 27 +++
1 file
From: Shannon Zhao
Add access handler which gets host value of PMCEID0 or PMCEID1 when
guest access these registers. Writing action to PMCEID0 or PMCEID1 is
UNDEFINED.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 27 +++
1 file changed, 23 insertions
From: Shannon Zhao
When we use tools like perf on host, perf passes the event type and the
id of this event type category to kernel, then kernel will map them to
hardware event number and write this number to PMU PMEVTYPER_EL0
register. When getting the event number in KVM, directly use raw
From: Shannon Zhao
When resetting vcpu, it needs to reset the PMU state to initial status.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/reset.c | 3 +++
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c | 17 +
3 files changed, 22 insertions(+)
diff --git a/arch/arm64
From: Shannon Zhao
We are about to trap and emulate accesses to each PMU register
individually. This adds the context offsets for the AArch64 PMU
registers.
Signed-off-by: Shannon Zhao
---
arch/arm64/include/asm/kvm_host.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a
From: Shannon Zhao
Add access handler which emulates writing and reading PMSWINC
register and add support for creating software increment event.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 18 +-
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 33
From: Shannon Zhao
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
disabled. When writing 1 to PMCR.P, reset all event counters, not
including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to
zero
From: Shannon Zhao
Here we plan to support virtual PMU for guest by full software
emulation, so define some basic structs and functions preparing for
futher steps. Define struct kvm_pmc for performance monitor counter and
struct kvm_pmu for performance monitor unit for each vcpu. According to
From: Shannon Zhao
Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. When reading PMSELR, return the PMSELR.SEL field to
guest.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions
From: Shannon Zhao
Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
the kvm_device_ops for it.
Signed-off-by: Shannon Zhao
---
Documentation/virtual/kvm/devices/arm-pmu.txt | 24 +
arch/arm64/include/uapi/asm/kvm.h | 4 +
include/linux/kvm_host.h
From: Shannon Zhao
This patchset adds guest PMU support for KVM on ARM64. It takes
trap-and-emulate approach. When guest wants to monitor one event, it
will be trapped by KVM and KVM will call perf_event API to create a perf
event and call relevant perf_event APIs to get the count value of event
From: Shannon Zhao
To use the ARMv8 PMU related register defines from the KVM code,
we move the relevant definitions to asm/pmu.h header file.
Signed-off-by: Anup Patel
Signed-off-by: Shannon Zhao
---
arch/arm64/include/asm/pmu.h | 67 ++
arch/arm64
From: Shannon Zhao
When calling perf_event_create_kernel_counter to create perf_event,
assign a overflow handler. Then when the perf event overflows, set the
corresponding bit of guest PMOVSSET register. If this counter is enabled
and its interrupt is enabled as well, kick the vcpu to sync the
From: Shannon Zhao
When KVM frees VCPU, it needs to free the perf_event of PMU.
Signed-off-by: Shannon Zhao
---
arch/arm/kvm/arm.c| 1 +
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 21 +
3 files changed, 24 insertions(+)
diff --git a/arch/arm/kvm/arm.c b
On 2015/12/17 17:38, Marc Zyngier wrote:
> On 17/12/15 08:41, Shannon Zhao wrote:
>> >
>> >
>> > On 2015/12/17 16:33, Marc Zyngier wrote:
>>> >> On Thu, 17 Dec 2015 15:22:50 +0800
>>> >> Shannon Zhao wrote:
>>> >>
On 2015/12/17 16:33, Marc Zyngier wrote:
> On Thu, 17 Dec 2015 15:22:50 +0800
> Shannon Zhao wrote:
>
>> >
>> >
>> > On 2015/12/17 4:33, Christoffer Dall wrote:
>>> > > On Wed, Dec 16, 2015 at 04:06:49PM +0800, Shannon Zhao wrote:
&g
On 2015/12/17 4:33, Christoffer Dall wrote:
> On Wed, Dec 16, 2015 at 04:06:49PM +0800, Shannon Zhao wrote:
>> Hi,
>>
>> On 2015/12/16 15:31, Shannon Zhao wrote:
>>>>>>>>> But in this case, you're returning an error if it is *not*
>>&g
On 2015/12/16 17:04, Marc Zyngier wrote:
> On 16/12/15 08:06, Shannon Zhao wrote:
>> > Hi,
>> >
>> > On 2015/12/16 15:31, Shannon Zhao wrote:
>>>>>>>>> >>>>>>>> But in this case, you're returning an error i
Hi,
On 2015/12/16 15:31, Shannon Zhao wrote:
>>>> >> > But in this case, you're returning an error if it is *not*
>>>> >> > initialized.
>>>> >> > I understand that in that case you cannot return an interrupt number
>>&
On 2015/12/16 4:47, Christoffer Dall wrote:
> On Tue, Dec 15, 2015 at 03:59:31PM +, Marc Zyngier wrote:
>> > On 15/12/15 15:50, Shannon Zhao wrote:
>>> > >
>>> > >
>>> > > On 2015/12/15 23:33, Marc Zyngier wrote:
>>>> &g
On 2015/12/15 22:58, Marc Zyngier wrote:
On 15/12/15 08:49, Shannon Zhao wrote:
>From: Shannon Zhao
>
>The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown.
>
>PMUSERENR_EL0 holds some bits which decide whether PMU registers can be
>accessed from EL0. Add som
On 2015/12/15 23:33, Marc Zyngier wrote:
On 15/12/15 08:49, Shannon Zhao wrote:
>From: Shannon Zhao
>
>Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
>the kvm_device_ops for it.
>
>Signed-off-by: Shannon Zhao
>---
> Documentation/virtual
On 2015/12/15 19:34, Marc Zyngier wrote:
On 15/12/15 08:49, Shannon Zhao wrote:
From: Shannon Zhao
To use the ARMv8 PMU related register defines from the KVM code,
we move the relevant definitions to asm/pmu.h header file.
Signed-off-by: Anup Patel
Signed-off-by: Shannon Zhao
---
arch
From: Shannon Zhao
We are about to trap and emulate accesses to each PMU register
individually. This adds the context offsets for the AArch64 PMU
registers.
Signed-off-by: Shannon Zhao
---
arch/arm64/include/asm/kvm_asm.h | 25 -
1 file changed, 20 insertions(+), 5
From: Shannon Zhao
To use the ARMv8 PMU related register defines from the KVM code,
we move the relevant definitions to asm/pmu.h header file.
Signed-off-by: Anup Patel
Signed-off-by: Shannon Zhao
---
arch/arm64/include/asm/pmu.h | 64 ++
arch/arm64
From: Shannon Zhao
Add access handler which emulates writing and reading PMSWINC
register and add support for creating software increment event.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 14 +-
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 32
From: Shannon Zhao
Add reset handler which gets host value of PMCR_EL0 and make writable
bits architecturally UNKNOWN except PMCR.E which is zero. Add an access
handler for PMCR.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 39 +--
1 file
From: Shannon Zhao
Add access handler which gets host value of PMCEID0 or PMCEID1 when
guest access these registers. Writing action to PMCEID0 or PMCEID1 is
ignored.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 26 ++
1 file changed, 22 insertions(+), 4
From: Shannon Zhao
When KVM frees VCPU, it needs to free the perf_event of PMU.
Signed-off-by: Shannon Zhao
---
arch/arm/kvm/arm.c| 1 +
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 21 +
3 files changed, 24 insertions(+)
diff --git a/arch/arm/kvm/arm.c b
From: Shannon Zhao
These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
which is mapped to PMEVTYPERn or PMCCFILTR.
The access handler translates all aarch32 register offsets to aarch64
ones and uses vcpu_sys_reg() to access their values to avoid taking care
of big endian.
When
From: Shannon Zhao
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
disabled. When writing 1 to PMCR.P, reset all event counters, not
including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to
zero
From: Shannon Zhao
Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMOVSSET or PMOVSCLR register.
When writing non-zero value to PMOVSSET, pend PMU interrupt.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm
From: Shannon Zhao
Here we plan to support virtual PMU for guest by full software
emulation, so define some basic structs and functions preparing for
futher steps. Define struct kvm_pmc for performance monitor counter and
struct kvm_pmu for performance monitor unit for each vcpu. According to
From: Shannon Zhao
Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. When reading PMSELR, return the PMSELR.SEL field to
guest.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 17 +++--
1 file changed, 15 insertions(+), 2
From: Shannon Zhao
When we use tools like perf on host, perf passes the event type and the
id of this event type category to kernel, then kernel will map them to
hardware event number and write this number to PMU PMEVTYPER_EL0
register. When getting the event number in KVM, directly use raw
From: Shannon Zhao
The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown.
PMUSERENR_EL0 holds some bits which decide whether PMU registers can be
accessed from EL0. Add some check helpers to handle the access from EL0.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 124
From: Shannon Zhao
Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
the kvm_device_ops for it.
Signed-off-by: Shannon Zhao
---
Documentation/virtual/kvm/devices/arm-pmu.txt | 16
arch/arm64/include/uapi/asm/kvm.h | 3 +
include/linux/kvm_host.h
From: Shannon Zhao
These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which
is mapped to PMEVCNTRn.
The access handler translates all aarch32 register offsets to aarch64
ones and uses vcpu_sys_reg() to access their values to avoid taking care
of big endian.
When reading these
From: Shannon Zhao
Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMINTENSET or PMINTENCLR register.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 29 +
1 file
From: Shannon Zhao
Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMCNTENSET or PMCNTENCLR register.
When writing to PMCNTENSET, call perf_event_enable to enable the perf
event. When writing to PMCNTENCLR
From: Shannon Zhao
When calling perf_event_create_kernel_counter to create perf_event,
assign a overflow handler. Then when the perf event overflows, set the
corresponding bit of guest PMOVSSET register. If this counter is enabled
and its interrupt is enabled as well, kick the vcpu to sync the
From: Shannon Zhao
When resetting vcpu, it needs to reset the PMU state to initial status.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/reset.c | 3 +++
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c | 17 +
3 files changed, 22 insertions(+)
diff --git a/arch/arm64
From: Shannon Zhao
This patchset adds guest PMU support for KVM on ARM64. It takes
trap-and-emulate approach. When guest wants to monitor one event, it
will be trapped by KVM and KVM will call perf_event API to create a perf
event and call relevant perf_event APIs to get the count value of event
On 2015/12/10 20:07, Marc Zyngier wrote:
> Hi Shannon,
>
> On 10/12/15 11:36, Shannon Zhao wrote:
>> > Hi Marc,
>> >
>> > On 2015/12/9 0:30, Marc Zyngier wrote:
>>> >> On 08/12/15 12:47, Shannon Zhao wrote:
>>>>> >>>>
Hi Marc,
On 2015/12/9 0:30, Marc Zyngier wrote:
> On 08/12/15 12:47, Shannon Zhao wrote:
>> > From: Shannon Zhao
>> >
>> > Since the reset value of PMEVCNTRn or PMCCNTR is UNKNOWN, use
>> > reset_unknown for its reset handler. Add access handler which emul
On 2015/12/9 1:03, Marc Zyngier wrote:
> On 08/12/15 12:47, Shannon Zhao wrote:
>> > From: Shannon Zhao
>> >
>> > The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown.
>> >
>> > Signed-off-by: Shannon Zhao
>> > ---
>>
On 2015/12/9 0:59, Marc Zyngier wrote:
>> > + }
>> > +
>> > + /* If all overflow bits are cleared, kick the vcpu to clear interrupt
>> > + * pending status.
>> > + */
>> > + if (val == 0)
>> > + kvm_vcpu_kick(vcpu);
> Do we really need to do so? This will be dropped on the next en
On 2015/12/9 0:42, Marc Zyngier wrote:
>> +void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable)
>> > +{
>> > + int i;
>> > + struct kvm_pmu *pmu = &vcpu->arch.pmu;
>> > + struct kvm_pmc *pmc;
>> > +
>> > + if (!all_enable)
>> > + return;
> You have the vcpu. C
On 2015/12/8 23:43, Marc Zyngier wrote:
> On 08/12/15 12:47, Shannon Zhao wrote:
>> From: Shannon Zhao
>> +/**
>> + * kvm_pmu_get_counter_value - get PMU counter value
>> + * @vcpu: The vcpu pointer
>> + * @select_idx: The counter index
>> + */
>> +
On 2015/12/8 22:10, Marc Zyngier wrote:
On 08/12/15 13:53, Will Deacon wrote:
On Tue, Dec 08, 2015 at 01:37:14PM +, Marc Zyngier wrote:
On 08/12/15 12:47, Shannon Zhao wrote:
From: Shannon Zhao
Here we plan to support virtual PMU for guest by full software
emulation, so define some
From: Shannon Zhao
When KVM frees VCPU, it needs to free the perf_event of PMU.
Signed-off-by: Shannon Zhao
---
arch/arm/kvm/arm.c| 1 +
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 21 +
3 files changed, 24 insertions(+)
diff --git a/arch/arm/kvm/arm.c b
From: Shannon Zhao
Accessing PMXEVTYPER register is mapped to the PMEVTYPERn or
PMCCFILTR which is selected by PMSELR. If the value of PMSELR is valid,
call kvm_pmu_set_counter_event_type to create a perf_event.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 55
From: Shannon Zhao
Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. As it doesn't need to deal with the accessing action
specially, it uses default case to emulate writing and reading PMSELR
register.
Signed-off-by: Shannon Zhao
---
arch/arm6
From: Shannon Zhao
To use the ARMv8 PMU related register defines from the KVM code,
we move the relevant definitions to asm/pmu.h header file.
Signed-off-by: Anup Patel
Signed-off-by: Shannon Zhao
---
arch/arm64/include/asm/pmu.h | 64 ++
arch/arm64
From: Shannon Zhao
Add reset handler which gets host value of PMCR_EL0 and make writable
bits architecturally UNKNOWN except PMCR.E to zero. Add a common access
handler for PMU registers which emulates writing and reading register
and add emulation for PMCR.
Signed-off-by: Shannon Zhao
From: Shannon Zhao
We are about to trap and emulate accesses to each PMU register
individually. This adds the context offsets for the AArch64 PMU
registers and their AArch32 counterparts.
Signed-off-by: Shannon Zhao
---
arch/arm64/include/asm/kvm_asm.h | 45
From: Shannon Zhao
When we use tools like perf on host, perf passes the event type and the
id of this event type category to kernel, then kernel will map them to
hardware event number and write this number to PMU PMEVTYPER_EL0
register. When getting the event number in KVM, directly use raw
From: Shannon Zhao
Accessing PMXEVCNTR register is mapped to the PMEVCNTRn or PMCCNTR which
is selected by PMSELR.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 44 ++--
1 file changed, 42 insertions(+), 2 deletions(-)
diff --git a/arch
From: Shannon Zhao
Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
the kvm_device_ops for it.
Signed-off-by: Shannon Zhao
---
Documentation/virtual/kvm/devices/arm-pmu.txt | 16 +
arch/arm64/include/uapi/asm/kvm.h | 3 +
include/linux/kvm_host.h
From: Shannon Zhao
Add access handler which emulates writing and reading PMSWINC
register and add support for creating software increment event.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 16 +++-
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 44
From: Shannon Zhao
This patchset adds guest PMU support for KVM on ARM64. It takes
trap-and-emulate approach. When guest wants to monitor one event, it
will be trapped by KVM and KVM will call perf_event API to create a perf
event and call relevant perf_event APIs to get the count value of event
From: Shannon Zhao
The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c830fde..80b66c0
From: Shannon Zhao
When calling perf_event_create_kernel_counter to create perf_event,
assign a overflow handler. Then when perf event overflows, call
kvm_vcpu_kick() to sync the interrupt.
Signed-off-by: Shannon Zhao
---
arch/arm/kvm/arm.c| 2 ++
include/kvm/arm_pmu.h | 2 ++
virt/kvm
From: Shannon Zhao
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
disabled. When writing 1 to PMCR.P, reset all event counters, not
including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to
zero
From: Shannon Zhao
Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMINTENSET or PMINTENCLR register.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 28
1 file
From: Shannon Zhao
Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMOVSSET or PMOVSCLR register.
When writing non-zero value to PMOVSSET, pend PMU interrupt. When the
value writing to PMOVSCLR is equal to the
From: Shannon Zhao
Add access handler which emulates writing and reading PMEVTYPERn or
PMCCFILTR register. When writing to PMEVTYPERn or PMCCFILTR, call
kvm_pmu_set_counter_event_type to create a perf_event for the selected
event type.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c
From: Shannon Zhao
Add reset handler which gets host value of PMCEID0 or PMCEID1. Since
write action to PMCEID0 or PMCEID1 is ignored, add a new case for this.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 29 +
1 file changed, 25 insertions(+), 4
From: Shannon Zhao
Since the reset value of PMEVCNTRn or PMCCNTR is UNKNOWN, use
reset_unknown for its reset handler. Add access handler which emulates
writing and reading PMEVCNTRn or PMCCNTR register. When reading
PMEVCNTRn or PMCCNTR, call perf_event_read_value to get the count value
of the
From: Shannon Zhao
When resetting vcpu, it needs to reset the PMU state to initial status.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/reset.c | 3 +++
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c | 17 +
3 files changed, 22 insertions(+)
diff --git a/arch/arm64
From: Shannon Zhao
Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMCNTENSET or PMCNTENCLR register.
When writing to PMCNTENSET, call perf_event_enable to enable the perf
event. When writing to PMCNTENCLR
From: Shannon Zhao
Here we plan to support virtual PMU for guest by full software
emulation, so define some basic structs and functions preparing for
futher steps. Define struct kvm_pmc for performance monitor counter and
struct kvm_pmu for performance monitor unit for each vcpu. According to
Hi Marc,
On 2015/12/7 22:55, Marc Zyngier wrote:
> On 07/12/15 14:31, Shannon Zhao wrote:
>> >
>> >
>> > On 2015/12/7 22:06, Marc Zyngier wrote:
>>> >> On 03/12/15 06:11, Shannon Zhao wrote:
>>>> >>> From: Shannon Zhao
>&g
Hi Marc,
On 2015/12/7 22:11, Marc Zyngier wrote:
Shannon,
On 03/12/15 06:11, Shannon Zhao wrote:
From: Shannon Zhao
This patchset adds guest PMU support for KVM on ARM64. It takes
trap-and-emulate approach. When guest wants to monitor one event, it
will be trapped by KVM and KVM will call
On 2015/12/7 21:56, Marc Zyngier wrote:
+static int kvm_arm_pmu_set_attr(struct kvm_device *dev,
>+ struct kvm_device_attr *attr)
>+{
>+ switch (attr->group) {
>+ case KVM_DEV_ARM_PMU_GRP_IRQ: {
>+ int __user *uaddr = (int __user *)(long)attr->addr;
>+
On 2015/12/7 22:06, Marc Zyngier wrote:
On 03/12/15 06:11, Shannon Zhao wrote:
From: Shannon Zhao
We are about to trap and emulate acccesses to each PMU register
s/acccesses/accesses/
individually. This adds the context offsets for the AArch64 PMU
registers and their AArch32
From: Shannon Zhao
Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMOVSSET or PMOVSCLR register.
When writing non-zero value to PMOVSSET, pend PMU interrupt. When the
value writing to PMOVSCLR is equal to the
From: Shannon Zhao
When calling perf_event_create_kernel_counter to create perf_event,
assign a overflow handler. Then when perf event overflows, call
kvm_vcpu_kick() to sync the interrupt.
Signed-off-by: Shannon Zhao
---
arch/arm/kvm/arm.c| 2 ++
include/kvm/arm_pmu.h | 2 ++
virt/kvm
From: Shannon Zhao
The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f5e0732..eb4fcf9
From: Shannon Zhao
Add access handler which emulates writing and reading PMEVCNTRn and
PMEVTYPERn.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 164 ++
1 file changed, 164 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch
From: Shannon Zhao
Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
the kvm_device_ops for it.
Signed-off-by: Shannon Zhao
---
Documentation/virtual/kvm/devices/arm-pmu.txt | 16 +
arch/arm64/include/uapi/asm/kvm.h | 3 +
include/linux/kvm_host.h
From: Shannon Zhao
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
disabled. When writing 1 to PMCR.P, reset all event counters, not
including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to
zero
From: Shannon Zhao
Here we plan to support virtual PMU for guest by full software
emulation, so define some basic structs and functions preparing for
futher steps. Define struct kvm_pmc for performance monitor counter and
struct kvm_pmu for performance monitor unit for each vcpu. According to
From: Shannon Zhao
Add access handler which emulates writing and reading PMSWINC
register and add support for creating software increment event.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 18 +-
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 44
From: Shannon Zhao
Add reset handler which gets host value of PMCEID0 or PMCEID1. Since
write action to PMCEID0 or PMCEID1 is ignored, add a new case for this.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 29 +
1 file changed, 25 insertions(+), 4
From: Shannon Zhao
When we use tools like perf on host, perf passes the event type and the
id of this event type category to kernel, then kernel will map them to
hardware event number and write this number to PMU PMEVTYPER_EL0
register. When getting the event number in KVM, directly use raw
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