On 07/01/16 14:12, Will Deacon wrote:
> On Thu, Jan 07, 2016 at 02:10:38PM +0000, Marc Zyngier wrote:
>> On 22/12/15 08:07, Shannon Zhao wrote:
>>> From: Shannon Zhao
>>>
>>> This patchset adds guest PMU support for KVM on ARM64. It takes
>>> trap-and-
On Tue, 22 Dec 2015 16:08:14 +0800
Shannon Zhao wrote:
> From: Shannon Zhao
>
> When KVM frees VCPU, it needs to free the perf_event of PMU.
>
> Signed-off-by: Shannon Zhao
Reviewed-by: Marc Zyngier
M.
--
Jazz is not dead. It just smells funny.
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To unsubscribe
On Tue, 22 Dec 2015 16:08:02 +0800
Shannon Zhao wrote:
> From: Shannon Zhao
>
> When we use tools like perf on host, perf passes the event type and the
> id of this event type category to kernel, then kernel will map them to
> hardware event number and write this number to PMU PMEVTYPER_EL0
> r
On 07/01/16 12:09, Shannon Zhao wrote:
>
>
> On 2015/12/22 16:08, Shannon Zhao wrote:
>> From: Shannon Zhao
>>
>> These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
>> which is mapped to PMEVTYPERn or PMCCFILTR.
>>
>> The access handler translates all aarch32 register offsets t
On 22/12/15 08:08, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add access handler which emulates writing and reading PMSWINC
> register and add support for creating software increment event.
>
> Signed-off-by: Shannon Zhao
> ---
> arch/arm64/kvm/sys_regs.c | 18 +-
> include/k
On 22/12/15 08:08, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use
> reset_unknown for its reset handler. Add a handler to emulate writing
> PMINTENSET or PMINTENCLR register.
>
> Signed-off-by: Shannon Zhao
> ---
> arch/arm64/kvm
On 22/12/15 08:08, Shannon Zhao wrote:
> From: Shannon Zhao
>
> These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which
> is mapped to PMEVCNTRn.
>
> The access handler translates all aarch32 register offsets to aarch64
> ones and uses vcpu_sys_reg() to access their values to avoi
On 22/12/15 08:08, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add access handler which gets host value of PMCEID0 or PMCEID1 when
> guest access these registers. Writing action to PMCEID0 or PMCEID1 is
> UNDEFINED.
>
> Signed-off-by: Shannon Zhao
> ---
> arch/arm64/kvm/sys_regs.c | 27 ++
On 22/12/15 08:08, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
> its reset handler. When reading PMSELR, return the PMSELR.SEL field to
> guest.
>
> Signed-off-by: Shannon Zhao
> ---
> arch/arm64/kvm/sys_regs.c | 16 +++
On 22/12/15 08:07, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add reset handler which gets host value of PMCR_EL0 and make writable
> bits architecturally UNKNOWN except PMCR.E which is zero. Add an access
> handler for PMCR.
>
> Signed-off-by: Shannon Zhao
> ---
> arch/arm64/kvm/sys_regs.c
On 22/12/15 08:07, Shannon Zhao wrote:
> From: Shannon Zhao
>
> We are about to trap and emulate accesses to each PMU register
> individually. This adds the context offsets for the AArch64 PMU
> registers.
>
> Signed-off-by: Shannon Zhao
Reviewed-by: Marc Zyngier
On 22/12/15 08:07, Shannon Zhao wrote:
> From: Shannon Zhao
>
> To use the ARMv8 PMU related register defines from the KVM code,
> we move the relevant definitions to asm/pmu.h header file.
>
> Signed-off-by: Anup Patel
> Signed-off-by: Shannon Zhao
Acked-by: Mar
On 22/12/15 08:08, Shannon Zhao wrote:
> From: Shannon Zhao
>
> This register resets as unknown in 64bit mode while it resets as zero
> in 32bit mode. Here we choose to reset it as zero for consistency.
>
> PMUSERENR_EL0 holds some bits which decide whether PMU registers can be
> accessed from E
fixes it by implementing section D1.10.2 of the ARMv8 ARM,
and in particular table D1-7 ("Vector offsets from vector table base
address"), which describes which vector to use depending on the source
exception level and type (synchronous, IRQ, FIQ or SError).
Signed-off-by: Marc Zyngier
ppens when, for example, there is GIC node in the device tree,
but it does not specify vGIC resources. Any other error code is still
treated as full stop because it might mean some really serious problems.
Signed-off-by: Pavel Fedin
Reviewed-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
arc
From: Vladimir Murzin
Since commit a987370 ("arm64: KVM: Fix stage-2 PGD allocation to have
per-page refcounting") there is no reference to S2_PGD_ORDER, so kill it
for the good.
Acked-by: Christoffer Dall
Signed-off-by: Vladimir Murzin
Signed-off-by: Marc Zyngier
---
arch/arm/i
From: Fengguang Wu
Acked-by: Christoffer Dall
Signed-off-by: Fengguang Wu
Signed-off-by: Marc Zyngier
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9bff63c..8e92b45 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6102,6 +6102,7 @@ M
lex Bennée
Acked-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/sys_regs.c | 58 +++
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 88adebf..eec3598 100644
From: Vladimir Murzin
The ARMv8.1 architecture extension allows to choose between 8-bit and
16-bit of VMID, so use this capability for KVM.
Reviewed-by: Christoffer Dall
Signed-off-by: Vladimir Murzin
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/kvm_arm.h | 2 +-
arch/arm/include
: Christoffer Dall
Signed-off-by: Vladimir Murzin
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/kvm_arm.h | 33 +
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
index b05bb5a..01d4d7a
architecture spec.
The spurious variables are removed in the process.
Reported-by: David Binderman
Reviewed-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
arch/arm/kvm/emulate.c | 74 ++
1 file changed, 38 insertions(+), 36 deletions(-)
diff
clean things up a bit.
Signed-off-by: Marc Zyngier
Acked-by: Christoffer Dall
---
arch/arm64/include/asm/kvm_asm.h | 76 -
arch/arm64/include/asm/kvm_emulate.h | 1 -
arch/arm64/include/asm/kvm_host.h| 81 +++-
arch/
In order to run C code in HYP, we must make sure that the kernel's
RO section is mapped into HYP (otherwise things break badly).
Signed-off-by: Marc Zyngier
Acked-by: Christoffer Dall
---
arch/arm/kvm/arm.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/kvm/arm.c b
As we've now switched to the new world switch implementation,
remove the weak attributes, as nobody is supposed to override
it anymore.
Acked-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/debug-sr.c | 5 ++---
arch/arm64/kvm/hyp/hyp-entry.S | 3 ---
arch/
As we've now rewritten most of our code-base in C, most of the
KVM-specific code in asm-offset.c is useless. Delete-time again!
Signed-off-by: Marc Zyngier
Acked-by: Christoffer Dall
---
arch/arm64/kernel/asm-offsets.c | 39 ---
1 file changed, 39 dele
Add the panic handler, together with the small bits of assembly
code to call the kernel's panic implementation.
Signed-off-by: Marc Zyngier
Reviewed-by: Christoffer Dall
---
arch/arm64/kvm/hyp/hyp-entry.S | 11 ++-
arch/arm64/kvm/hyp/hyp.h | 1 +
arch/arm64/kvm/hyp/swi
Add the entry points for HYP mode (both for hypercalls and
exception handling).
Signed-off-by: Marc Zyngier
Reviewed-by: Christoffer Dall
---
arch/arm64/kvm/hyp/Makefile| 1 +
arch/arm64/kvm/hyp/hyp-entry.S | 203 +
2 files changed, 204 insertions
This is it. We remove all of the code that has now been rewritten.
Signed-off-by: Marc Zyngier
Acked-by: Christoffer Dall
---
arch/arm64/kvm/Makefile |2 -
arch/arm64/kvm/hyp.S| 1081 +--
arch/arm64/kvm/vgic-v2-switch.S | 134
ws the new implementation to be overriden by the
old one, and everything still work.
At a later point, we'll be able to simply drop the old code, and
everything will hopefully keep working, thanks to the aliases we
have just added. This also saves us repainting all the callers.
Signed-off-by: Marc
that
outputs a brief sequence of code that in turn can be patched, allowing
an alternative function to be selected.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/hyp.h | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/kvm/hyp/hyp.h b/arch/arm64/kvm/
Implement the fpsimd save restore, keeping the lazy part in
assembler (as returning to C would be overkill).
Signed-off-by: Marc Zyngier
Reviewed-by: Christoffer Dall
---
arch/arm64/kvm/hyp/Makefile| 1 +
arch/arm64/kvm/hyp/entry.S | 32 +++-
arch/arm64/kvm
Contrary to the previous patch, the guest entry is fairly different
from its assembly counterpart, mostly because it is only concerned
with saving/restoring the GP registers, and nothing else.
Reviewed-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/Makefile | 1
Implement the core of the world switch in C. Not everything is there
yet, and there is nothing to re-enter the world switch either.
But this already outlines the code structure well enough.
Signed-off-by: Marc Zyngier
Reviewed-by: Christoffer Dall
---
arch/arm64/kvm/hyp/Makefile | 1 +
arch
Implement the TLB handling as a direct translation of the assembly
code version.
Signed-off-by: Marc Zyngier
Reviewed-by: Christoffer Dall
---
arch/arm64/kvm/hyp/Makefile | 1 +
arch/arm64/kvm/hyp/entry.S | 1 +
arch/arm64/kvm/hyp/tlb.c| 73
Implement the debug save restore as a direct translation of
the assembly code version.
Signed-off-by: Marc Zyngier
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reviewed-by: Christoffer Dall
---
arch/arm64/kvm/hyp/Makefile | 1 +
arch/arm64/kvm/hyp/debug-sr.c | 137
Implement the 32bit system register save/restore as a direct
translation of the assembly code version.
Signed-off-by: Marc Zyngier
Reviewed-by: Christoffer Dall
---
arch/arm64/kvm/hyp/hyp.h | 2 ++
arch/arm64/kvm/hyp/sysreg-sr.c | 47 ++
2 files
Implement the system register save/restore as a direct translation of
the assembly code version.
Signed-off-by: Marc Zyngier
Reviewed-by: Christoffer Dall
---
arch/arm64/kvm/hyp/Makefile| 1 +
arch/arm64/kvm/hyp/hyp.h | 3 ++
arch/arm64/kvm/hyp/sysreg-sr.c | 90
Implement the vgic-v3 save restore as a direct translation of
the assembly code version.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/Makefile | 1 +
arch/arm64/kvm/hyp/hyp.h| 3 +
arch/arm64/kvm/hyp/vgic-v3-sr.c | 226
3 files
Implement the timer save restore as a direct translation of
the assembly code version.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/Makefile | 1 +
arch/arm64/kvm/hyp/hyp.h | 3 ++
arch/arm64/kvm/hyp/timer-sr.c| 71
We store GICv3 LRs in reverse order so that the CPU can save/restore
them in rever order as well (don't ask why, the design is crazy),
and yet generate memory traffic that doesn't completely suck.
We need this macro to be available to the C version of save/restore.
Signed-off-by: Ma
From: Amit Tomar
It would add guest exit statistics to debugfs, this can be helpful
while measuring KVM performance.
[ Renamed some of the field names - Christoffer ]
Signed-off-by: Amit Singh Tomar
Signed-off-by: Christoffer Dall
---
arch/arm/include/asm/kvm_host.h | 6 ++
arch/arm/
From: Mark Rutland
Rather than crafting custom macros for reading/writing each system
register provide generics accessors, read_sysreg and write_sysreg, for
this purpose.
Signed-off-by: Mark Rutland
Acked-by: Catalin Marinas
Cc: Suzuki Poulose
Cc: Will Deacon
Signed-off-by: Marc Zyngier
In order to expose the various EL2 services that are private to
the hypervisor, add a new hyp.h file.
So far, it only contains mundane things such as section annotation
and VA manipulation.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/hyp.h | 33 +
1 file
From: Jisheng Zhang
vgic_io_ops is only referenced within vgic.c, so it can be declared
static.
Signed-off-by: Jisheng Zhang
Signed-off-by: Christoffer Dall
---
virt/kvm/arm/vgic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c
in
Implement the vgic-v2 save restore (mostly) as a direct translation
of the assembly code version.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/Makefile | 1 +
arch/arm64/kvm/hyp/Makefile | 5 +++
arch/arm64/kvm/hyp/hyp.h| 3 ++
arch/arm64/kvm/hyp/vgic-v2-sr.c | 84
s cleanups
Amit Tomar (1):
KVM: arm/arm64: Count guest exit due to various reasons
Fengguang Wu (1):
MAINTAINERS: add git URL for KVM/ARM
Jisheng Zhang (1):
KVM: arm/arm64: vgic: make vgic_io_ops static
Marc Zyngier (23):
arm64: KVM: Add a HYP-specific header file
good news is that so far, we never do this, so I believe the
current code is safe. But the PMU code is soon going to exercise that
path, and I'd rather plug it sooner that later.
Thanks,
M.
Marc Zyngier (2):
arm: KVM: Do not update PC if the trap handler has updated it
arm64: KV
efore the access is performed,
and checking if it has moved or not before incrementing it.
Reported-by: Shannon Zhao
Signed-off-by: Marc Zyngier
---
arch/arm/kvm/coproc.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/cop
e the access is performed,
and checking if it has moved or not before incrementing it.
Reported-by: Shannon Zhao
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/sys_regs.c | 73 +++
1 file changed, 36 insertions(+), 37 deletions(-)
diff --git a/arch/
ut if not active in the LRs
we just return if *any* IRQ is active on the VCPU in question.
This is of course bogus, as we should check if the specific IRQ in
quesiton is active on the distributor instead.
Reported-by: Eric Auger
Acked-by: Marc Zyngier
Signed-off-by: Christoffer Dall
Signed-o
Hi Paolo,
We have a one line fix for the VGIC this time around, fixing a patch
that went in -rc2. Oh well. Hopefully this is the last one for v4.4.
And yes, the right patch is following the pull-request this time...
Please pull!
Thanks,
M.
The following changes since commit 0de58f85287
Idiot alert, sending the wrong patch...
On 18/12/15 13:00, Marc Zyngier wrote:
> Hi Paolo,
>
> We have a one line fix for the VGIC this time around, fixing a patch
> that went in -rc2. Oh well. Hopefully this is the last one for v4.4.
>
> Please pull!
Or don't, act
Improve handling of multi-source SGIs: instead of only inserting
one source per SGI per run, try to insert them all at once.
Hopefully this is a rare case.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic.c | 30 ++
1 file changed, 26 insertions(+), 4
Hi Paolo,
We have a one line fix for the VGIC this time around, fixing a patch
that went in -rc2. Oh well. Hopefully this is the last one for v4.4.
Please pull!
Thanks,
M.
The following changes since commit 0de58f852875a0f0dcfb120bb8433e4e73c7803b:
ARM/arm64: KVM: correct PTE uncach
On Fri, 18 Dec 2015 14:38:43 +0300
Pavel Fedin wrote:
> Before commit 662d9715840aef44dcb573b0f9fab9e8319c868a
> ("arm/arm64: KVM: Kill CONFIG_KVM_ARM_{VGIC,TIMER}") is was possible to
> compile the kernel without vGIC and vTimer support. Commit message says
> about possibility to detect vGIC sup
On 17/12/15 16:28, Alex Bennée wrote:
>
> Marc Zyngier writes:
>
>> The debug trapping code is pretty heavy on the "inline" attribute,
>> but most functions are actually referenced in the sysreg tables,
>> making the inlining imposible.
>>
>>
On 17/12/15 15:22, Mark Rutland wrote:
> On Tue, Dec 15, 2015 at 04:49:27PM +0800, Shannon Zhao wrote:
>> From: Shannon Zhao
>>
>> When we use tools like perf on host, perf passes the event type and the
>> id of this event type category to kernel, then kernel will map them to
>> hardware event num
On 17/12/15 10:10, Shannon Zhao wrote:
>
>
> On 2015/12/17 17:38, Marc Zyngier wrote:
>> On 17/12/15 08:41, Shannon Zhao wrote:
>>>>
>>>>
>>>> On 2015/12/17 16:33, Marc Zyngier wrote:
>>>>>> On Thu, 17 Dec 2015 15:22:50 +0800
&
On 17/12/15 08:41, Shannon Zhao wrote:
>
>
> On 2015/12/17 16:33, Marc Zyngier wrote:
>> On Thu, 17 Dec 2015 15:22:50 +0800
>> Shannon Zhao wrote:
>>
>>>>
>>>>
>>>> On 2015/12/17 4:33, Christoffer Dall wrote:
>>>>&
On Thu, 17 Dec 2015 15:22:50 +0800
Shannon Zhao wrote:
>
>
> On 2015/12/17 4:33, Christoffer Dall wrote:
> > On Wed, Dec 16, 2015 at 04:06:49PM +0800, Shannon Zhao wrote:
> >> Hi,
> >>
> >> On 2015/12/16 15:31, Shannon Zhao wrote:
> > But in this case, you're returning an error if it is
lex Bennée
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/sys_regs.c | 58 +++
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 88adebf..eec3598 100644
--- a/arch/arm64/kvm/sys_re
On 16/12/15 08:06, Shannon Zhao wrote:
> Hi,
>
> On 2015/12/16 15:31, Shannon Zhao wrote:
But in this case, you're returning an error if it is *not* initialized.
I understand that in that case you cannot return an interrupt number
(-1
would be weird), but retur
On 15/12/15 15:59, Shannon Zhao wrote:
>
>
> On 2015/12/15 22:58, Marc Zyngier wrote:
>> On 15/12/15 08:49, Shannon Zhao wrote:
>>>> From: Shannon Zhao
>>>>
>>>> The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown.
>>>&
On 15/12/15 15:50, Shannon Zhao wrote:
>
>
> On 2015/12/15 23:33, Marc Zyngier wrote:
>> On 15/12/15 08:49, Shannon Zhao wrote:
>>>> From: Shannon Zhao
>>>>
>>>> Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
>
On 15/12/15 08:49, Shannon Zhao wrote:
> From: Shannon Zhao
>
> This patchset adds guest PMU support for KVM on ARM64. It takes
> trap-and-emulate approach. When guest wants to monitor one event, it
> will be trapped by KVM and KVM will call perf_event API to create a perf
> event and call releva
On 15/12/15 08:49, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
> the kvm_device_ops for it.
>
> Signed-off-by: Shannon Zhao
> ---
> Documentation/virtual/kvm/devices/arm-pmu.txt | 16
> arch/arm64/include/uapi/asm/
On 15/12/15 08:49, Shannon Zhao wrote:
> From: Shannon Zhao
>
> When calling perf_event_create_kernel_counter to create perf_event,
> assign a overflow handler. Then when the perf event overflows, set the
> corresponding bit of guest PMOVSSET register. If this counter is enabled
> and its interru
On 15/12/15 08:49, Shannon Zhao wrote:
> From: Shannon Zhao
>
> The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown.
>
> PMUSERENR_EL0 holds some bits which decide whether PMU registers can be
> accessed from EL0. Add some check helpers to handle the access from EL0.
>
> Signed-off-b
On 15/12/15 08:49, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add access handler which emulates writing and reading PMSWINC
> register and add support for creating software increment event.
>
> Signed-off-by: Shannon Zhao
> ---
> arch/arm64/kvm/sys_regs.c | 14 +-
> include/kvm/a
On 15/12/15 08:49, Shannon Zhao wrote:
> From: Shannon Zhao
>
> These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
> which is mapped to PMEVTYPERn or PMCCFILTR.
>
> The access handler translates all aarch32 register offsets to aarch64
> ones and uses vcpu_sys_reg() to access th
On 15/12/15 08:49, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add access handler which gets host value of PMCEID0 or PMCEID1 when
> guest access these registers. Writing action to PMCEID0 or PMCEID1 is
> ignored.
>
> Signed-off-by: Shannon Zhao
> ---
> arch/arm64/kvm/sys_regs.c | 26
On 15/12/15 08:49, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use
> reset_unknown for its reset handler. Add a handler to emulate writing
> PMOVSSET or PMOVSCLR register.
>
> When writing non-zero value to PMOVSSET, pend PMU interrupt.
On 15/12/15 08:49, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use
> reset_unknown for its reset handler. Add a handler to emulate writing
> PMINTENSET or PMINTENCLR register.
>
> Signed-off-by: Shannon Zhao
> ---
> arch/arm64/kvm
On 15/12/15 08:49, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use
> reset_unknown for its reset handler. Add a handler to emulate writing
> PMCNTENSET or PMCNTENCLR register.
>
> When writing to PMCNTENSET, call perf_event_enable t
On 15/12/15 08:49, Shannon Zhao wrote:
> From: Shannon Zhao
>
> These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which
> is mapped to PMEVCNTRn.
>
> The access handler translates all aarch32 register offsets to aarch64
> ones and uses vcpu_sys_reg() to access their values to avoi
On 15/12/15 08:49, Shannon Zhao wrote:
> From: Shannon Zhao
>
> These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
> which is mapped to PMEVTYPERn or PMCCFILTR.
>
> The access handler translates all aarch32 register offsets to aarch64
> ones and uses vcpu_sys_reg() to access th
On 15/12/15 08:49, Shannon Zhao wrote:
> From: Shannon Zhao
>
> To use the ARMv8 PMU related register defines from the KVM code,
> we move the relevant definitions to asm/pmu.h header file.
>
> Signed-off-by: Anup Patel
> Signed-off-by: Shannon Zhao
> ---
> arch/arm64/include/asm/pmu.h | 64
On 15/12/15 10:57, Bhushan Bharat wrote:
>
>
>> -Original Message-----
>> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
>> Sent: Tuesday, December 15, 2015 3:50 PM
>> To: Bhushan Bharat-R65777 ;
>> kvm...@lists.cs.columbia.edu; kvm@vger.kernel.org; linu
On 15/12/15 09:53, Bhushan Bharat wrote:
> Hi Mark,
>
>> -Original Message-----
>> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
>> Sent: Tuesday, December 15, 2015 3:05 PM
>> To: Bhushan Bharat-R65777 ;
>> kvm...@lists.cs.columbia.edu; kv
On 15/12/15 03:46, Bhushan Bharat wrote:
>
> Hi All,
>
> I am running "iperf" in KVM guest on ARM64 machine and observing below crash.
>
> =
> $iperf -c 3.3.3.3 -P 4 -t 0 -i 5 -w 90k
>
> Client connecting to
Hi Mario,
On 11/12/15 03:24, Mario Smarduch wrote:
> Hi Marc,
>
> On 12/7/2015 2:53 AM, Marc Zyngier wrote:
>> Implement the system register save/restore as a direct translation of
>> the assembly code version.
>>
>> Signed-off-by: Marc Zyngier
>> Reviewe
rm/vgic.c
> @@ -1114,7 +1114,7 @@ bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu,
> struct irq_phys_map *map)
> return true;
> }
>
> - return dist_active_irq(vcpu);
> + return vgic_irq_is_active(vcpu, map->virt_irq);
> }
>
>
Hi Shannon,
On 10/12/15 11:36, Shannon Zhao wrote:
> Hi Marc,
>
> On 2015/12/9 0:30, Marc Zyngier wrote:
>> On 08/12/15 12:47, Shannon Zhao wrote:
>>>> From: Shannon Zhao
>>>>
>>>> Since the reset value of PMEVCNTRn or PMCCNTR is UNKNOWN, use
&
On Wed, 9 Dec 2015 17:18:02 +0800
Shannon Zhao wrote:
>
>
> On 2015/12/9 1:03, Marc Zyngier wrote:
> > On 08/12/15 12:47, Shannon Zhao wrote:
> >> > From: Shannon Zhao
> >> >
> >> > The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_
On Wed, 9 Dec 2015 16:35:58 +0800
Shannon Zhao wrote:
>
>
> On 2015/12/9 0:42, Marc Zyngier wrote:
> >> +void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool
> >> all_enable)
> >> > +{
> >> > +int i;
&g
On Wed, 9 Dec 2015 15:38:09 +0800
Shannon Zhao wrote:
>
>
> On 2015/12/8 23:43, Marc Zyngier wrote:
> > On 08/12/15 12:47, Shannon Zhao wrote:
> >> From: Shannon Zhao
> >> +/**
> >> + * kvm_pmu_get_counter_value - get PMU counter value
> >&g
Shannon,
On 08/12/15 12:47, Shannon Zhao wrote:
> From: Shannon Zhao
>
> This patchset adds guest PMU support for KVM on ARM64. It takes
> trap-and-emulate approach. When guest wants to monitor one event, it
> will be trapped by KVM and KVM will call perf_event API to create a perf
> event and c
On 08/12/15 12:47, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
> the kvm_device_ops for it.
>
> Signed-off-by: Shannon Zhao
> ---
> Documentation/virtual/kvm/devices/arm-pmu.txt | 16 +
> arch/arm64/include/uapi/asm/
On 08/12/15 12:47, Shannon Zhao wrote:
> From: Shannon Zhao
>
> According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
> enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
> disabled. When writing 1 to PMCR.P, reset all event counters, not
> including PMCCNTR, to zero
On 08/12/15 12:47, Shannon Zhao wrote:
> From: Shannon Zhao
>
> When calling perf_event_create_kernel_counter to create perf_event,
> assign a overflow handler. Then when perf event overflows, call
> kvm_vcpu_kick() to sync the interrupt.
Please update the commit message, things have changed qui
On 08/12/15 12:47, Shannon Zhao wrote:
> From: Shannon Zhao
>
> The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown.
>
> Signed-off-by: Shannon Zhao
> ---
> arch/arm64/kvm/sys_regs.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/kvm/sys_re
On 08/12/15 12:47, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use
> reset_unknown for its reset handler. Add a new case to emulate writing
> PMOVSSET or PMOVSCLR register.
>
> When writing non-zero value to PMOVSSET, pend PMU interrupt
On 08/12/15 12:47, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use
> reset_unknown for its reset handler. Add a new case to emulate writing
> PMCNTENSET or PMCNTENCLR register.
>
> When writing to PMCNTENSET, call perf_event_enable
On 08/12/15 12:47, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Accessing PMXEVCNTR register is mapped to the PMEVCNTRn or PMCCNTR which
> is selected by PMSELR.
>
> Signed-off-by: Shannon Zhao
> ---
> arch/arm64/kvm/sys_regs.c | 44 ++--
> 1 file change
On 08/12/15 12:47, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Since the reset value of PMEVCNTRn or PMCCNTR is UNKNOWN, use
> reset_unknown for its reset handler. Add access handler which emulates
> writing and reading PMEVCNTRn or PMCCNTR register. When reading
> PMEVCNTRn or PMCCNTR, call per
On 08/12/15 12:47, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add access handler which emulates writing and reading PMEVTYPERn or
> PMCCFILTR register. When writing to PMEVTYPERn or PMCCFILTR, call
> kvm_pmu_set_counter_event_type to create a perf_event for the selected
> event type.
>
> Signe
On 08/12/15 12:47, Shannon Zhao wrote:
> From: Shannon Zhao
>
> When we use tools like perf on host, perf passes the event type and the
> id of this event type category to kernel, then kernel will map them to
> hardware event number and write this number to PMU PMEVTYPER_EL0
> register. When gett
On 08/12/15 12:47, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add reset handler which gets host value of PMCEID0 or PMCEID1. Since
> write action to PMCEID0 or PMCEID1 is ignored, add a new case for this.
>
> Signed-off-by: Shannon Zhao
> ---
> arch/arm64/kvm/sys_regs.c | 29
On 08/12/15 13:53, Will Deacon wrote:
> On Tue, Dec 08, 2015 at 01:37:14PM +0000, Marc Zyngier wrote:
>> On 08/12/15 12:47, Shannon Zhao wrote:
>>> From: Shannon Zhao
>>>
>>> Here we plan to support virtual PMU for guest by full software
>>> emulatio
On 08/12/15 12:47, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Here we plan to support virtual PMU for guest by full software
> emulation, so define some basic structs and functions preparing for
> futher steps. Define struct kvm_pmc for performance monitor counter and
> struct kvm_pmu for perfo
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