t; Signed-off-by: Andrey Smetanin
> CC: Paolo Bonzini
> CC: Gleb Natapov
> CC: James Hogan
> CC: Paolo Bonzini
> CC: Paul Burton
> CC: Ralf Baechle
> CC: Alexander Graf
> CC: Christian Borntraeger
> CC: Cornelia Huck
> CC: linux-m...@linux-mips.org
> CC: kvm-
Implement saving and restoring to KVM state of the Processor ID (PRid)
CP0 register. This allows QEMU to control the PRid exposed to the guest
instead of using the default set by KVM.
Signed-off-by: James Hogan
Reviewed-by: Leon Alrae
Cc: Paolo Bonzini
Cc: Aurelien Jarno
---
target-mips
nd so that QEMU can
save/restore the guest modifiable bits (Config5.FRE, Config5.UFR,
Config5.UFE). The FCSR/FIR registers and the floating point registers
are now saved/restored (depending on the FR mode bit).
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
Ch
.MSAP) and so that QEMU can
save/restore the guest modifiable bits (Config5.MSAEn). The MSACSR/MSAIR
registers and the MSA vector registers are now saved/restored. Since the
FP registers are a subset of the vector registers, they are omitted if
the guest has MSA.
Signed-off-by: James Hogan
Cc: Paolo
them on migration/savevm.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
Changes in v2:
- Fix line wrapping of kvm_mips_get_one_reg() calls from Config4 and
Config5 (Leon).
- Change (1 << x) to (1U << x) in important places to avoid compil
Rename kvm_mips_{get,put}_one_reg64() to kvm_mips_{get,put}_one_ureg64()
since they take an int64_t pointer, and add separate signed 64-bit
accessors. These will be used for double precision floating point
registers.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien
Add KVM register access functions for the uint32_t type. This is
required for FP and MSA control registers, which are represented as
unsigned 32-bit integers.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
Changes in v3:
- Fix big endian (the pointer passed
The DPRINTFs in cpu_mips_io_interrupts_pending() and kvm_arch_pre_run()
are particularly noisy during normal execution, and also not
particularly helpful. Remove them so that more important debug messages
can be more easily seen.
Signed-off-by: James Hogan
Reviewed-by: Leon Alrae
Cc: Paolo
s from Config4 and
Config5 in patch 5 (Leon).
- Change (1 << x) to (1U << x) in important places in patch 5, 8 & 9 to
avoid compiler undefined behaviour (Leon).
James Hogan (7):
mips/kvm: Remove a couple of noisy DPRINTFs
mips/kvm: Implement PRid CP0 register
mips/kv
Hi Paolo.
On Thu, Dec 17, 2015 at 11:39:14AM +0100, Paolo Bonzini wrote:
>
>
> On 17/12/2015 00:49, James Hogan wrote:
> > This patchset contains a bunch of miscellaneous cleanups (which are
> > mostly trivial) for MIPS KVM & MIPS headers, such as:
> > - Style
A bunch of misc whitespace and style fixes within arch/mips/kvm/.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: kvm@vger.kernel.org
Cc: linux-m...@linux-mips.org
---
arch/mips/Kconfig| 3 ++-
arch/mips/include/asm/kvm_host.h | 2 +-
arch
The module init and exit functions have no need to be global, so make
them static.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: kvm@vger.kernel.org
Cc: linux-m...@linux-mips.org
---
arch/mips/kvm/mips.c | 4 ++--
1 file changed, 2 insertions(+), 2
Export symbols only to GPL modules to match other KVM symbols in
virt/kvm/ and arch/*/kvm/.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
arch/mips/kvm/callback.c | 2 +-
arch/mips/kvm/tlb.c | 36
The first argument to set_except_vector is the ExcCode, which we now
have definitions for. Lets make use of them.
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: linux-m...@linux-mips.org
---
arch/mips/kernel/cpu-bugs64.c | 8 +++
arch/mips/kernel/traps.c | 52
Add a few missing trap codes, and drop a couple of unused definitions
for virtual coherency that aren't in the latest architecture revisions.
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: linux-m...@linux-mips.org
---
arch/mips/include/asm/mipsregs.h | 12 ++--
1 file change
The CAUSEB_DC and CAUSEF_DC definitions used by KVM are defined in
asm/kvm_host.h, but all the other Cause register field definitions are
found in asm/mipsregs.h.
Lets reunite the DC bit definitions with its friends in mipsregs.h.
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: Paolo Bonzini
Move the Cause.ExcCode trap code definitions from kvm_host.h to
mipsregs.h, since they describe architectural bits rather than KVM
specific constants, and change the prefix from T_ to EXCCODE_.
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: Paolo Bonzini
Cc: Gleb Natapov
Cc: linux-m...@linux
I've pretty much been maintaining KVM for MIPS for a while now. Lets
make it more official (and make sure I get Cc'd on relevant patches).
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: Paolo Bonzini
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
MAINT
Make consistent use of uint8_t in MMIO handling code.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
arch/mips/kvm/emulate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips
Add missing newline to end of kvm_err string when guest PMAP couldn't be
allocated.
Signed-off-by: James Hogan
Cc: Gleb Natapov
Cc: Paolo Bonzini
Cc: Ralf Baechle
Cc: kvm@vger.kernel.org
Cc: linux-m...@linux-mips.org
---
arch/mips/kvm/mips.c | 2 +-
1 file changed, 1 insertion(+), 1 del
The function kvm_mips_host_tlb_inv_index() is unused, so drop it
completely.
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: Paolo Bonzini
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
arch/mips/include/asm/kvm_host.h | 1 -
arch/mips/kvm/tlb.c | 37
into parts where it makes sense to do so, and
add masks for the Cache and Op field within the cache op.
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: linux-m...@linux-mips.org
---
arch/mips/include/asm/cacheops.h | 106 +++
1 file changed, 64 insertions(+), 42
Drop the custom cache operation code definitions used by KVM for
emulating guest CACHE instructions, and switch to use the existing
definitions in .
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Gleb Natapov
Cc: Ralf Baechle
Cc: kvm@vger.kernel.org
Cc: linux-m...@linux-mips.org
---
arch
uction set
manual, and wait_op was already added to inst.h in commit b0a3eae2b943
("MIPS: inst.h: define COP0 wait op"), merged in v3.16-rc1.
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: Paolo Bonzini
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
arch/m
Some definitions in the MIPS asm/kvm_host.h are completely unused, so
lets drop them.
MS_TO_NS is no longer used since commit e30492bbe95a ("MIPS: KVM:
Rewrite count/compare timer emulation"). The others don't appear ever to
have been used.
Signed-off-by: James Hogan
Cc: Paolo Bo
/ so they can be shared with the rest of
arch/mips. Specifically COP0 register bits, exception codes, cache
ops, & instruction opcodes.
- Add MAINTAINERS entry for MIPS KVM.
Due to the interaction with other arch/mips/ code, I think it makes
sense for these to go via the MIPS tree.
James H
offset
of the specific register within the commpage.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
arch/mips/kvm/dyntrans.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/arch
. Note, this assembly is specific to the trap &
emulate implementation of KVM, so it doesn't need to check the
supervisor bit as that mode is not implemented in the guest.
Fixes: b680f70fc111 ("KVM/MIPS32: Entry point for trampolining to...")
Signed-off-by: James Hogan
Cc: Ralf
ranch
emulation.")
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: Paolo Bonzini
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
Signed-off-by: Paolo Bonzini
Signed-off-by: James Hogan
---
arch/mips/kvm/kvm_mips_emul.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
s: 669e846e6c4e ("KVM/MIPS32: MIPS arch specific APIs for KVM")
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: Paolo Bonzini
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
Signed-off-by: Paolo Bonzini
Signed-off-by: James Hogan
---
arch/mips/kvm/kvm_mips.c | 5
. Note, this assembly is specific to the trap &
emulate implementation of KVM, so it doesn't need to check the
supervisor bit as that mode is not implemented in the guest.
Fixes: b680f70fc111 ("KVM/MIPS32: Entry point for trampolining to...")
Signed-off-by: James Hogan
Cc: Ralf
Hi Paolo,
On Wed, Nov 11, 2015 at 03:43:14PM +0100, Paolo Bonzini wrote:
> On 11/11/2015 15:21, James Hogan wrote:
> > A few misc MIPS KVM fixes for issues that have been around since the
> > code was merged in v3.10.
> >
> > James Hogan (3):
> > MIPS
The immediate field of the CACHE instruction is signed, so ensure that
it gets sign extended by casting it to an int16_t rather than just
masking the low 16 bits.
Fixes: e685c689f3a8 ("KVM/MIPS32: Privileged instruction/target branch
emulation.")
Signed-off-by: James Hogan
Cc: Ralf B
A few misc MIPS KVM fixes for issues that have been around since the
code was merged in v3.10.
James Hogan (3):
MIPS: KVM: Fix ASID restoration logic
MIPS: KVM: Fix CACHE immediate offset sign extension
MIPS: KVM: Uninit VCPU in vcpu_create error path
arch/mips/kvm/emulate.c | 2 +-
arch
late implementation of KVM, so it doesn't need to check the
supervisor bit as that mode is not implemented in the guest.
Fixes: b680f70fc111 ("KVM/MIPS32: Entry point for trampolining to...")
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: Paolo Bonzini
Cc: Gleb Natapov
Cc: linux-m..
KVM")
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: Paolo Bonzini
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
Cc: # 3.10.x-
---
arch/mips/kvm/mips.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kvm/mips.c b/arch/mips/kvm/
ikely to need to be used from assembly code.
Fixes: "MIPS: CPS: Early debug using an ns16550-compatible UART"
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: Paul Burton
Cc: Paolo Bonzini
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
Ralf: Please can you
On Mon, Nov 02, 2015 at 05:26:42PM +0800, Haozhong Zhang wrote:
> The value of the migrated vcpu's TSC rate is determined as below.
> 1. If a TSC rate is specified by the cpu option 'tsc-freq', then this
> user-specified value will be used.
> 2. If neither a user-specified TSC rate nor a migr
On 09/07/15 14:59, Peter Maydell wrote:
> On 9 July 2015 at 12:52, Leon Alrae wrote:
>> On 09/07/2015 10:17, James Hogan wrote:
>>> These two patches fix build errors for the MIPS TCG backend and MIPS
>>> KVM.
>>>
>>> Please could they be applied for
ation of the previous
definition
Also update the MIPS_C0_{32,64} macros to utilise definitions more
recently added to the asm-mips/kvm.h header.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
Cc: kvm@vger.kernel.org
---
target-mips/kvm.c | 15 ++--
These two patches fix build errors for the MIPS TCG backend and MIPS
KVM.
Please could they be applied for v2.4.
James Hogan (2):
tcg/mips: Fix build error from merged memop+mmu_idx parameter
mips/kvm: Sync with newer MIPS KVM headers
target-mips/kvm.c | 15 ++-
tcg/mips
Hi Paolo,
On 24/04/15 11:26, James Hogan wrote:
> A couple of small fixes for accessing 32-bit KVM registers on big
> endian, and to sign extend struct kvm_regs registers so as to work on
> MIPS64 hosts.
>
> James Hogan (2):
> mips/kvm: Fix Big endian 32-bit register access
From: Nicholas Mc Guire
commit ed9244e6c534612d2b5ae47feab2f55a0d4b4ced upstream.
Fix possible unintended sign extension in unsigned MMIO loads by casting
to uint16_t in the case of mmio_needed != 2.
Signed-off-by: Nicholas Mc Guire
Reviewed-by: James Hogan
Tested-by: James Hogan
Cc: Gleb
Hi stable folk,
On 08/05/15 15:16, James Hogan wrote:
> On 07/05/15 13:47, Nicholas Mc Guire wrote:
>> Fix possible unintended sign extension in unsigned MMIO loads by casting
>> to uint16_t in the case of mmio_needed != 2.
>>
>> Signed-off-by: Nicholas Mc Guire
>
In case we're running on a 64-bit host, be sure to sign extend the
general purpose registers and hi/lo/pc before writing them to KVM, so as
to take advantage of MIPS32/MIPS64 compatibility.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
Cc: kvm@vger.kerne
Fix access to 32-bit registers on big endian targets. The pointer passed
to the kernel must be for the actual 32-bit value, not a temporary
64-bit value, otherwise on big endian systems the kernel will only
interpret the upper half.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
A couple of small fixes for accessing 32-bit KVM registers on big
endian, and to sign extend struct kvm_regs registers so as to work on
MIPS64 hosts.
James Hogan (2):
mips/kvm: Fix Big endian 32-bit register access
mips/kvm: Sign extend registers written to KVM
target-mips/kvm.c | 21
e
> reply to this email.
>
> For more information about the 3.13.y-ckt tree, see
> https://wiki.ubuntu.com/Kernel/Dev/ExtendedStable
>
> Thanks.
> -Kamal
>
> --
>
> From 7adee277d64254de602234e7e53691d729f5e50c Mon Sep 17 00:00:00 2001
> From: Jame
anch in the MIPS
tree first.
--------
James Hogan (24):
MIPS: lose_fpu(): Disable FPU when MSA enabled
Revert "MIPS: Don't assume 64-bit FP registers for context switch"
MIPS: MSA: Fix big-endian FPR_IDX implementation
Merge branch &#x
Now that the code is in place for KVM to support FPU in MIPS KVM guests,
wire up the new KVM_CAP_MIPS_FPU capability.
For backwards compatibility, the capability must be explicitly enabled
in order to detect or make use of the FPU from the guest.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc
-bit half native endian as
the kernel uses internally.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: Jonathan Corbet
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: linux-...@vger.kernel.org
if the hardware supports MSA vector
partitioning, since the extra support cannot be tested yet and it
extends the state that the userland program would have to save.
Signed-off-by: James Hogan
Acked-by: Paolo Bonzini
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: Jonathan Corbet
Cc: linux-m...@linux
main guest FPU support.
- Patches 16..20 add the main guest MSA support (structured like 11.15).
James Hogan (20):
MIPS: KVM: Handle MSA Disabled exceptions from guest
MIPS: Clear [MSA]FPE CSR.Cause after notify_die()
MIPS: KVM: Handle TRAP exceptions from guest kernel
MIPS: KVM: Implement P
On 26/03/15 13:58, Paolo Bonzini wrote:
>
>
> On 11/03/2015 15:44, James Hogan wrote:
>> Now that the code is in place for KVM to support MIPS SIMD Architecutre
>> (MSA) in MIPS guests, wire up the new KVM_CAP_MIPS_MSA capability.
>>
>> For backwards comp
nd so that QEMU can
save/restore the guest modifiable bits (Config5.FRE, Config5.UFR,
Config5.UFE). The FCSR/FIR registers and the floating point registers
are now saved/restored (depending on the FR mode bit).
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
Ch
Add KVM register access functions for the uint32_t type. This is
required for FP and MSA control registers, which are represented as
unsigned 32-bit integers.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
target-mips/kvm.c | 29
ility"
https://patchwork.kernel.org/patch/5986151/
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
Changes in v2:
- Removed most of patch 7 and updates to linux-headers/linux/kvm.h from
patches 8 and 9, and put in this
.MSAP) and so that QEMU can
save/restore the guest modifiable bits (Config5.MSAEn). The MSACSR/MSAIR
registers and the MSA vector registers are now saved/restored. Since the
FP registers are a subset of the vector registers, they are omitted if
the guest has MSA.
Signed-off-by: James Hogan
Cc: Paolo
to utilise definitions more
recently added to the asm-mips/kvm.h header.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
Changes in v2:
- Add the changes to MIPS_CP0_{32,64} macros from v1 patch 7, since the
rest of that patch is now unnecessary and the chang
them on migration/savevm.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
Changes in v2:
- Fix line wrapping of kvm_mips_get_one_reg() calls from Config4 and
Config5 (Leon).
- Change (1 << x) to (1U << x) in important places to avoid compil
The DPRINTFs in cpu_mips_io_interrupts_pending() and kvm_arch_pre_run()
are particularly noisy during normal execution, and also not
particularly helpful. Remove them so that more important debug messages
can be more easily seen.
Signed-off-by: James Hogan
Reviewed-by: Leon Alrae
Cc: Paolo
Implement saving and restoring to KVM state of the Processor ID (PRid)
CP0 register. This allows QEMU to control the PRid exposed to the guest
instead of using the default set by KVM.
Signed-off-by: James Hogan
Reviewed-by: Leon Alrae
Cc: Paolo Bonzini
Cc: Aurelien Jarno
---
target-mips
Rename kvm_mips_{get,put}_one_reg64() to kvm_mips_{get,put}_one_ureg64()
since they take an int64_t pointer, and add separate signed 64-bit
accessors. These will be used for double precision floating point
registers.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien
.
- Fix line wrapping of kvm_mips_get_one_reg() calls from Config4 and
Config5 in patch 5 (Leon).
- Change (1 << x) to (1U << x) in important places in patch 5, 8 & 9 to
avoid compiler defined behaviour (Leon).
James Hogan (9):
DONT APPLY: linux-headers: Update MIPS KVM headers
mi
On 12/03/15 16:44, Paolo Bonzini wrote:
>
>
> On 11/03/2015 16:22, James Hogan wrote:
>> diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
>> index 12045a11c036..410eb158f564 100644
>> --- a/linux-headers/linux/kvm.h
>> +++ b/linux-header
On 12/03/15 16:41, Leon Alrae wrote:
> On 11/03/2015 15:22, James Hogan wrote:
>> Implement saving and restoring to KVM state of the Config CP0 registers
>> (namely Config, Config1, Config2, Config3, Config4, and Config5). These
>> control the features available to a guest, an
.MSAP) and so that QEMU can
save/restore the guest modifiable bits (Config5.MSAEn). The MSACSR/MSAIR
registers and the MSA vector registers are now saved/restored. Since the
FP registers are a subset of the vector registers, they are omitted if
the guest has MSA.
Signed-off-by: James Hogan
Cc: Paolo
The KVM_REG_MIPS_COUNT_* definitions are now included in
linux-headers/asm-mips/kvm.h since commit b061808d39fa ("linux-headers:
update linux headers to kvm/next"), therefore the duplicate definitions
in target-mips/kvm.c can now be dropped.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
The DPRINTFs in cpu_mips_io_interrupts_pending() and kvm_arch_pre_run()
are particularly noisy during normal execution, and also not
particularly helpful. Remove them so that more important debug messages
can be more easily seen.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc
Add KVM register access functions for the uint32_t type. This is
required for FP and MSA control registers, which are represented as
unsigned 32-bit integers.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
target-mips/kvm.c | 29
Rename kvm_mips_{get,put}_one_reg64() to kvm_mips_{get,put}_one_ureg64()
since they take an int64_t pointer, and add separate signed 64-bit
accessors. These will be used for double precision floating point
registers.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien
state, but that's fine) when it is next used in
the new FP mode.
Any change to the Config5.FRE bit is immediately updated in the host
state so that the guest can get the relevant exceptions right away for
single-precision FPU operations.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Paul
guest registers as provided by the VZ ASE.
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: Paolo Bonzini
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
arch/mips/include/asm/kvm_host.h | 2 ++
arch/mips/kvm/tlb.c | 6 ++
arch/mips/kvm/trap_emul.c
-bit half native endian as
the kernel uses internally.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: Jonathan Corbet
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: linux-...@vger.kernel.org
FPU.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
arch/mips/include/asm/kvm_host.h | 16 +
arch/mips/kvm/emulate.c | 71
arch
The information messages when the KVM module is loaded and unloaded are
a bit pointless and out of line with other architectures, so lets drop
them.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
arch
if the hardware supports MSA vector
partitioning, since the extra support cannot be tested yet and it
extends the state that the userland program would have to save.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: Jonathan Corbet
Cc: linux-m...@linux-mips.org
not to change bits without fully
handling the possible extra state that may then exist and which the
guest may begin to use and depend on.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
Documentation
Implement access to the guest Processor Identification CP0 register
using the KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls. This allows the
owning process to modify and read back the value that is exposed to the
guest in this register.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Ralf Baechle
Now that the code is in place for KVM to support FPU in MIPS KVM guests,
wire up the new KVM_CAP_MIPS_FPU capability.
For backwards compatibility, the capability must be explicitly enabled
in order to detect or make use of the FPU from the guest.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc
print
the usual BUG message and stack trace.
Implement handling of the trap exception so that it gets passed to the
guest and the user is left with a more useful log message.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: kvm@vger.kernel.org
Cc: linux-m...@linu
guest (because no guest FPU was supported), but the
hypervisor can now handle them if the guest has its FPU enabled by
restoring the guest FPU context and enabling the FPU.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: linux-m...@linux
d for when Status.CU1 is set while FR=0 and
the MSA state is live. In this case we are at risk of getting reserved
instruction exceptions if we try and save the MSA state, so we lose the
MSA state sooner while MSA is still usable.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Paul Burton
Cc:
them on migration/savevm.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
target-mips/kvm.c | 108 ++
1 file changed, 108 insertions(+)
diff --git a/target-mips/kvm.c b/target-mips/kvm.c
index 730c67e247d8
nd so that QEMU can
save/restore the guest modifiable bits (Config5.FRE, Config5.UFR,
Config5.UFE). The FCSR/FIR registers and the floating point registers
are now saved/restored (depending on the FR mode bit).
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
Add the new floating point and MIPS SIMD Architecture (MSA) KVM register
definitions to kvm.c.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
target-mips/kvm.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a
Implement saving and restoring to KVM state of the Processor ID (PRid)
CP0 register. This allows QEMU to control the PRid exposed to the guest
instead of using the default set by KVM.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
target-mips/kvm.c | 11
mments welcome.
James Hogan (9):
mips/kvm: Drop KVM_REG_MIPS_COUNT_* definitions
mips/kvm: Remove a couple of noisy DPRINTFs
mips/kvm: Implement PRid CP0 register
mips/kvm: Implement Config CP0 registers
mips/kvm: Support unsigned KVM registers
mips/kvm: Support signed 64-bit KVM regist
e MSA Disabled
exception by emulating a Reserved Instruction exception in the guest,
via a new handle_msa_disabled() KVM callback.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
Cc: #
PU
state will become architecturally UNPREDICTABLE (change of FR mode) to
force a reload of [stale] context in the new FR mode.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
arch/mips/include/
Various semi-used definitions exist in kvm_host.h for the default guest
config registers. Remove them and use the appropriate values directly
when initialising the Config registers.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc
gned-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
arch/mips/include/asm/kvm_host.h | 4 +-
arch/mips/include/uapi/asm/kvm.h | 115 ++-
2 files changed, 66 insertions(+)
mode of the guest, with each
sized access showing what the guest would see with an equivalent access,
and like the architecture they may become UNPREDICTABLE if the FR mode
is changed. When FR=0, odd doubles are inaccessible as they do not exist
in that mode.
Signed-off-by: James Hogan
Cc: Paolo
Sort the registers in the kvm_mips_get_reg() switch by register number,
which puts ERROREPC after the CONFIG registers.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
arch/mips/kvm/mips.c | 6 +++---
1
ase to get hit.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
arch/mips/include/asm/kvm_host.h | 21 -
arch/mips/kernel/asm-offsets.c | 1 +
arch/mips/kvm/Makefile |
be able to restore
FCSR/MSACSR registers with exceptions pending.
- Patches 3..10 add various misc KVM improvements and cleanups, most of
which the later patches depend on.
- Patches 11..15 add the main guest FPU support.
- Patches 16..20 add the main guest MSA support (structured like 11.1
argument (msacsr) and calls notify_die() with the new DIE_MSAFP,
allowing die notifiers to be informed of MSA FPEs too.
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: Paul Burton
Cc: Paolo Bonzini
Cc: Gleb Natapov
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
arch/mips/i
MIPS: Don't leak FPU/DSP to guest"):
ERROR: "_save_fp" [arch/mips/kvm/kvm.ko] undefined!
Signed-off-by: James Hogan
Fixes: f798217dfd03 (KVM: MIPS: Don't leak FPU/DSP to guest)
Cc: Paolo Bonzini
Cc: Ralf Baechle
Cc: Paul Burton
Cc: Gleb Natapov
Cc: kvm@vger.kernel.org
Hi Greg,
On Tue, Mar 03, 2015 at 10:13:26PM -0800, Greg Kroah-Hartman wrote:
> 3.14-stable review patch. If anyone has any objections, please let me know.
>
> --
>
> From: James Hogan
>
> commit f798217dfd038af981a18bbe4bc57027a08bb182 upstream.
>
ther than being lazily restored, so for that
it is simpler to just clear the MX bit again when re-entering the guest.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Ralf Baechle
Cc: Sanjay Lal
Cc: Gleb Natapov
Cc: kvm@vger.kernel.org
Cc: linux-m...@linux-mips.org
Cc: # v3.10+: 044f0f03eca0:
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