Paul Mackerras writes:
> The reference (R) and change (C) bits in a HPT entry can be set by
> hardware at any time up until the HPTE is invalidated and the TLB
> invalidation sequence has completed. This means that when removing
> a HPTE, we need to read the HPTE after the invalidation sequence
pte can get updated from other CPUs as part of multiple activities
like THP split, huge page collapse, unmap. We need to make sure we
don't reload the pte value again and again for different checks.
Signed-off-by: Aneesh Kumar K.V
---
Note:
This is posted previously as part of
This patch remove helpers which we had used only once in the code.
Limiting page table walk variants help in ensuring that we won't
end up with code walking page table with wrong assumptions.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable.h | 21 -
We don't support real-mode areas now that 970 support is removed.
Remove the remaining details of rma from the code. Also rename
rma_setup_done to hpte_setup_done to better reflect the changes.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_host.h | 3 +--
arch/powerp
later with code movements. We also document why a
non-barrier variant is ok in performance critical path.
Signed-off-by: Aneesh Kumar K.V
---
Changes from V1:
* Rebase to latest upstream
arch/powerpc/kvm/book3s_64_mmu_hv.c | 10 +-
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 15 ++
neesh Kumar K.V
---
Changes from V1:
* Rebase to latest upstream
arch/powerpc/include/asm/kvm_book3s_64.h | 14 ++
arch/powerpc/kvm/book3s_64_mmu_hv.c | 25 ++---
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 25 +
3 files changed, 33 inser
Hi,
Any update on this patch. We could drop patch 3. Any feedback on 1 and 2
?.
-aneesh
"Aneesh Kumar K.V" writes:
> This patch adds helper routine for lock and unlock hpte and use
> the same for rest of the code. We don't change any locking rules in this
> patch. In
"Suresh E. Warrier" writes:
> This patch adds trace points in the guest entry and exit code and also
> for exceptions handled by the host in kernel mode - hypercalls and page
> faults. The new events are added to /sys/kernel/debug/tracing/events
> under a new subsystem called kvm_hv.
>
"Aneesh Kumar K.V" writes:
> Paul Mackerras writes:
>
>> The B (segment size) field in the RB operand for the tlbie
>> instruction is two bits, which we get from the top two bits of
>> the first doubleword of the HPT entry to be invalidated. These
>> b
not rely on guests doing
> this.
>
> Cc: Aneesh Kumar K.V
> Signed-off-by: Paul Mackerras
Reviewed-by: Aneesh Kumar K.V
> ---
> arch/powerpc/include/asm/kvm_book3s_64.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/include/
neesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s_64.h | 14 ++
arch/powerpc/kvm/book3s_64_mmu_hv.c | 25 ++---
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 27 ++-
3 files changed, 34 insertions(+), 32 deletions(-)
diff --git a/arch/po
Minor cleanup
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
index 78e689b066f1..2922f8d127ff
later with code movements. We also document why a
non-barrier variant is ok in performance critical path.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_64_mmu_hv.c | 10 +-
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 15 ++-
2 files changed, 15 insertions(+), 10 deletion
Herrenschmidt
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_64_mmu_hv.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c
b/arch/powerpc/kvm/book3s_64_mmu_hv.c
index d40770248b6a..cebb86bc4a37 100644
--- a/arch/powerpc/kvm
We use cma reserved area for creating guest hash page table.
Don't do the reservation in non-hypervisor mode. This avoids unnecessary
CMA reservation when booting with limited memory configs like
fadump and kdump.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_hv_builtin.
s get_order() with order_base_2() (round-up version of ilog2).
>
> Suggested-by: Paul Mackerras
> Cc: Alexander Graf
> Cc: Aneesh Kumar K.V
> Cc: Joonsoo Kim
> Cc: Benjamin Herrenschmidt
> Signed-off-by: Alexey Kardashevskiy
Reviewed-by: Aneesh Kumar K.V
> ---
&
s get_order() with ilog2().
Should we round it up ? ie, ilog2(kvm_rma_pages - 1) + 1 ?
>
> Suggested-by: Paul Mackerras
> Cc: Alexander Graf
> Cc: Aneesh Kumar K.V
> Cc: Joonsoo Kim
> Cc: Benjamin Herrenschmidt
> Cc:
Why stable ? We merged it this merge window.
Paul Mackerras writes:
> On Sun, Jun 29, 2014 at 04:47:31PM +0530, Aneesh Kumar K.V wrote:
>> This makes it consistent with h_enter where we clear the key
>> bits. We also want to use virtual page class key protection mechanism
>> for indicating host page fault. For that
Paul Mackerras writes:
> On Sun, Jun 29, 2014 at 04:47:34PM +0530, Aneesh Kumar K.V wrote:
>> As per ISA, we first need to mark hpte invalid (V=0) before we update
>> the hpte lower half bits. With virtual page class key protection mechanism
>> we want
>> to send any
Paul Mackerras writes:
> On Sun, Jun 29, 2014 at 04:47:33PM +0530, Aneesh Kumar K.V wrote:
>> We want to use virtual page class key protection mechanism for
>> indicating a MMIO mapped hpte entry or a guest hpte entry that is swapped out
>> in the host. Those hptes will be m
Benjamin Herrenschmidt writes:
> On Sun, 2014-06-29 at 16:47 +0530, Aneesh Kumar K.V wrote:
>
>> To achieve the above we use virtual page calss protection mechanism for
>> covering (2) and (3). For both the above case we mark the hpte
>> valid, but associate the page
When calculating the lower bits of AVA field, use the shift
count based on the base page size. Also add the missing segment
size and remove stale comment.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s_64.h | 6 --
arch/powerpc/kvm/book3s_hv.c | 6
updating the hpte. To track that add a vm specific atomic
variable that we check in the fault path to always send the fault
to host.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s_64.h | 1 +
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/kernel/asm
y. We mark those HPTEs
invalid and use the software defined bit, HPTE_V_VRMA, to differentiate
them.
NOTE: We still need to handle protection fault in host so that a
write to KSM shared page is handled in the host.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s_64.h
Since we do don't support virtual page class key protection mechanism in
the guest, we should not find a keyfault that needs to be forwarded to
the guest. So remove the dead code.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_64_mmu_hv.c | 9 -
arch/powerp
VALID with places where we want to
check whether the hpte is host mapped. This patch enables a closer
review for such a change.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s_64.h | 36
arch/powerpc/kvm/book3s_64_mmu_hv.c
munmap(c, length);
}
}
Without Fix:
--
[root@qemu-pr-host ~]# time ./pfault
real0m8.438s
user0m0.855s
sys 0m7.540s
[root@qemu-pr-host ~]#
With Fix:
[root@qemu-pr-host ~]# time ./pfault
real0m7.833s
user0m0.782s
sys 0m7.038s
[root@qemu-pr-host ~]#
virtual page class protection mechanism for
the guest. This will not have any impact for PAPR linux guest because
Linux guest currently don't use virtual page class key protection model
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 12
1 file chang
We will use this to set HPTE_V_VRMA bit in the later patch. This also
make sure we clear the hpte bits only when called via hcall.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_64_mmu_hv.c | 15 +--
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 8 ++--
2 files changed, 19
When calculating the lower bits of AVA field, use the shift
count based on the base page size. Also add the missing segment
size and remove stale comment.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s_64.h | 6 --
arch/powerpc/kvm/book3s_hv.c | 6
Alexander Graf writes:
> We use ABIv2 on Little Endian systems which gets rid of the dotted function
> names. Branch to the actual functions when we see such a system.
>
> Signed-off-by: Alexander Graf
As per patches sent by anton we don't need this. We can branch to the
function rathen than th
Joonsoo Kim writes:
> On Sat, Jun 14, 2014 at 12:55:39PM +0530, Aneesh Kumar K.V wrote:
>> Joonsoo Kim writes:
>>
>> > Currently, there are two users on CMA functionality, one is the DMA
>> > subsystem and the other is the kvm on powerpc. They have their own
Joonsoo Kim writes:
> On Sat, Jun 14, 2014 at 02:23:59PM +0530, Aneesh Kumar K.V wrote:
>> Joonsoo Kim writes:
>>
>> > Now, we have general CMA reserved area management framework,
>> > so use it for future maintainabilty. There is no functional change.
>
Alexander Graf writes:
> So far we've been able to successfully run HV KVM on big endian hosts, but
> once you dive into little endian land things start to fall apart.
>
> This patch set enables HV KVM for little endian hosts. This should be the
> final piece left missing to get little endian sys
page size in kvmppc_hv_find_lock_hpte.
Signed-off-by: Aneesh Kumar K.V
---
Changes from V1:
* Remove obsolete comment from the code
* Update commit message
arch/powerpc/include/asm/kvm_book3s_64.h | 19 +--
arch/powerpc/kvm/book3s_64_mmu_hv.c | 2 +-
arch/powerpc/kvm
Joonsoo Kim writes:
> Currently, there are two users on CMA functionality, one is the DMA
> subsystem and the other is the kvm on powerpc. They have their own code
> to manage CMA reserved area even if they looks really similar.
> From my guess, it is caused by some needs on bitmap management. Kv
ity for following generalization.
>
> Signed-off-by: Joonsoo Kim
Reviewed-by: Aneesh Kumar K.V
>
> diff --git a/drivers/base/dma-contiguous.c b/drivers/base/dma-contiguous.c
> index bc4c171..9bc9340 100644
> --- a/drivers/base/dma-contiguous.c
> +++ b/drivers/base/dma-conti
;
> v2: There is no big change from v1 in mm/cma.c. Mostly renaming.
>
> Acked-by: Michal Nazarewicz
> Signed-off-by: Joonsoo Kim
Reviewed-by: Aneesh Kumar K.V
>
> diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
> index 00e13ce..4eac559 100644
> --- a/driver
;
> v2: There is no big change from v1 in mm/cma.c. Mostly renaming.
>
> Acked-by: Michal Nazarewicz
> Signed-off-by: Joonsoo Kim
Reviewed-by: Aneesh Kumar K.V
>
> diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
> index 00e13ce..4eac559 100644
> --- a/driver
c/kvm/book3s_hv_cma.c
> deleted file mode 100644
> index d9d3d85..000
> --- a/arch/powerpc/kvm/book3s_hv_cma.c
> +++ /dev/null
> @@ -1,240 +0,0 @@
> -/*
> - * Contiguous Memory Allocator for ppc KVM hash pagetable based on CMA
> - * for DMA mapping framework
> - *
> -
Joonsoo Kim writes:
> Now, we have general CMA reserved area management framework,
> so use it for future maintainabilty. There is no functional change.
>
> Acked-by: Michal Nazarewicz
> Acked-by: Paolo Bonzini
> Signed-off-by: Joonsoo Kim
Need this. We may want to keep the VM_BUG_ON by movin
Joonsoo Kim writes:
> Currently, there are two users on CMA functionality, one is the DMA
> subsystem and the other is the kvm on powerpc. They have their own code
> to manage CMA reserved area even if they looks really similar.
> From my guess, it is caused by some needs on bitmap management. Kv
Joonsoo Kim
Reviewed-by: Aneesh Kumar K.V
>
> diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c
> b/arch/powerpc/kvm/book3s_hv_builtin.c
> index 28ec226..97613ea 100644
> --- a/arch/powerpc/kvm/book3s_hv_builtin.c
> +++ b/arch/powerpc/kvm/book3s_hv_builtin.c
> @@ -1
Joonsoo Kim writes:
> We can remove one call sites for clear_cma_bitmap() if we first
> call it before checking error number.
>
> Signed-off-by: Joonsoo Kim
Reviewed-by: Aneesh Kumar K.V
>
> diff --git a/mm/cma.c b/mm/cma.c
> index 1e1b017..01a0713 100644
> --- a/m
Alexander Graf writes:
> On 13.06.14 16:28, Aneesh Kumar K.V wrote:
>> Alexander Graf writes:
>>
>>> On 13.06.14 09:23, Aneesh Kumar K.V wrote:
>>>> With guest supporting Multiple page size per segment (MPSS),
>>>> hpte_page_size returns actual p
Alexander Graf writes:
> On 13.06.14 09:23, Aneesh Kumar K.V wrote:
>> With guest supporting Multiple page size per segment (MPSS),
>> hpte_page_size returns actual page size used. Add a new function to
>> return base page size and use that to compare against the the page si
With guest supporting Multiple page size per segment (MPSS),
hpte_page_size returns actual page size used. Add a new function to
return base page size and use that to compare against the the page size
calculated from SLB
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s_64
gion.
>
> Signed-off-by: Joonsoo Kim
Reviewed-by: Aneesh Kumar K.V
>
> diff --git a/drivers/base/dma-contiguous.c b/drivers/base/dma-contiguous.c
> index 8a44c82..bc4c171 100644
> --- a/drivers/base/dma-contiguous.c
> +++ b/drivers/base/dma-contiguous.c
> @@ -32,6
g patches.
> This separation helps us not to touch DMA APIs while extending
> core functions.
>
> Signed-off-by: Joonsoo Kim
Reviewed-by: Aneesh Kumar K.V
>
> diff --git a/drivers/base/dma-contiguous.c b/drivers/base/dma-contiguous.c
> index fb0cdce..8a44c82 100644
> --- a/driv
Joonsoo Kim writes:
> We should free memory for bitmap when we find zone mis-match,
> otherwise this memory will leak.
>
> Additionally, I copy code comment from ppc kvm's cma code to notify
> why we need to check zone mis-match.
>
> Signed-off-by: Joonsoo Kim
Rev
Joonsoo Kim writes:
> We don't need explicit 'CMA:' prefix, since we already define prefix
> 'cma:' in pr_fmt. So remove it.
>
> And, some logs print function name and others doesn't. This looks
> bad to me, so I unify log format to print function name consistently.
>
> Lastly, I add one more deb
Alexander Graf writes:
> On 05.06.14 14:08, Aneesh Kumar K.V wrote:
>> virtual time base register is a per VM, per cpu register that needs
>> to be saved and restored on vm exit and entry. Writing to VTB is not
>> allowed in the privileged mode.
>>
>> Signed-
Alexander Graf writes:
> On 05.06.14 14:08, Aneesh Kumar K.V wrote:
>> We don't have SMT support yet, hence we should not find a doorbell
>> message generated
>>
>> Signed-off-by: Aneesh Kumar K.V
>> ---
>> arch/powerpc/kvm/book3s_emulate.c | 1
o
> obj-$(CONFIG_ZBUD) += zbud.o
> obj-$(CONFIG_ZSMALLOC) += zsmalloc.o
> obj-$(CONFIG_GENERIC_EARLY_IOREMAP) += early_ioremap.o
> +obj-$(CONFIG_CMA)+= cma.o
> diff --git a/mm/cma.c b/mm/cma.c
> new file mode 100644
> index 000..0dae88d
> --- /dev/null
Alexander Graf writes:
> On 05.06.14 17:50, Aneesh Kumar K.V wrote:
>> Alexander Graf writes:
>>
>>> On 05.06.14 14:08, Aneesh Kumar K.V wrote:
>>>> virtual time base register is a per VM, per cpu register that needs
>>>> to be saved and rest
Paolo Bonzini writes:
> Il 03/06/2014 09:02, Michal Nazarewicz ha scritto:
>> On Tue, Jun 03 2014, Joonsoo Kim wrote:
>>> Now, we have general CMA reserved area management framework,
>>> so use it for future maintainabilty. There is no functional change.
>>>
>>> Signed-off-by: Joonsoo Kim
>>
>>
Alexander Graf writes:
> On 05.06.14 14:21, Alexander Graf wrote:
>>
>> On 05.06.14 14:08, Aneesh Kumar K.V wrote:
>>> We don't have SMT support yet, hence we should not find a doorbell
>>> message generated
>>>
>>> Signed-off-by: Aneesh Ku
Alexander Graf writes:
> On 05.06.14 14:08, Aneesh Kumar K.V wrote:
>> virtual time base register is a per VM, per cpu register that needs
>> to be saved and restored on vm exit and entry. Writing to VTB is not
>> allowed in the privileged mode.
>>
>>
Since we don't support SMT yet, we should always find zero in
Directed privileged doorbell exception state register.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_emulate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kvm/book3s_emulate.c
b/arch/powerp
Writing to IC is not allowed in the privileged mode.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/kvm/book3s.c | 6 ++
arch/powerpc/kvm/book3s_emulate.c | 3 +++
arch/powerpc/kvm/book3s_hv.c| 6 --
arch/powerpc/kvm
virtual time base register is a per VM, per cpu register that needs
to be saved and restored on vm exit and entry. Writing to VTB is not
allowed in the privileged mode.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/include/asm/reg.h | 15
We don't have SMT support yet, hence we should not find a doorbell
message generated
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_emulate.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_emulate.c
b/arch/powerp
This patchset adds support for emulating VTB, IC and Doorbell features in P8.
Doorbell support is dummy since we don't support SMT cores with PR-KVM.
-aneesh
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"Aneesh Kumar K.V" writes:
> Paul Mackerras writes:
>
>> On Tue, Jun 03, 2014 at 05:46:11PM +0530, Aneesh Kumar K.V wrote:
>>> We use time base for PURR and SPURR emulation with PR KVM since we
>>> are emulating a single threaded core. When using time bas
hypervisor resource.
Signed-off-by: Aneesh Kumar K.V
---
Changes from V1:
Move the purr/spurr update to happen only once in case of exit with preemption
enabled.
arch/powerpc/include/asm/kvm_book3s.h | 2 --
arch/powerpc/include/asm/kvm_host.h | 4 ++--
arch/powerpc/kvm/book3s_emulate.
Paul Mackerras writes:
> On Tue, Jun 03, 2014 at 05:46:11PM +0530, Aneesh Kumar K.V wrote:
>> We use time base for PURR and SPURR emulation with PR KVM since we
>> are emulating a single threaded core. When using time base
>> we need to make sure that we don't accumul
hypervisor resource.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s.h | 2 --
arch/powerpc/include/asm/kvm_host.h | 4 ++--
arch/powerpc/kvm/book3s_emulate.c | 16
arch/powerpc/kvm/book3s_pr.c | 10 ++
4 files changed, 20 inserti
Use make_dsisr instead of open coding it. This also have
the added benefit of handling alignment interrupt on additional
instructions.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/disassemble.h | 34 +
arch/powerpc/kernel/align.c| 34
Although it's optional, IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V
---
Changes from V5:
* Split the patch to two and also update commit message
arch/powerpc/kvm/book3s_emulate.c | 7 +
Paul Mackerras writes:
> On Sun, May 04, 2014 at 10:56:08PM +0530, Aneesh Kumar K.V wrote:
>> With debug option "sleep inside atomic section checking" enabled we get
>> the below WARN_ON during a PR KVM boot. This is because upstream now
>> have PREEMPT_COUNT
nd the actual page size correctly from the
HPTE entry.
Signed-off-by: Aneesh Kumar K.V
---
Changes from V1:
* Update commit message
* Rename variables as per review feedback
arch/powerpc/include/asm/kvm_book3s_64.h | 146 ++-
arch/powerpc/kvm/book3s_hv.c | 7 +
Alexander Graf writes:
> On 05/06/2014 05:06 PM, Aneesh Kumar K.V wrote:
>> Alexander Graf writes:
>>
>>> On 05/06/2014 11:26 AM, Benjamin Herrenschmidt wrote:
>>>> On Tue, 2014-05-06 at 11:12 +0200, Alexander Graf wrote:
>>>>
>> .
>&
le we still have plenty of space
available in CMA.
This patch addresses this issue by first trying hash page table
allocation from CMA's reserved region before falling back to the normal
page allocator. So if we run out of memory, we really are out of memory.
Signed-off-by: Aneesh
Alexander Graf writes:
> On 05/06/2014 11:26 AM, Benjamin Herrenschmidt wrote:
>> On Tue, 2014-05-06 at 11:12 +0200, Alexander Graf wrote:
>>
.
I updated the commit message as below. Let me know if this is ok.
KVM: PPC: BOOK3S: HV: THP support for guest
On recent IBM Power CP
Although it's optional IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V
---
* Changes from V4
* Update comments around using fault_dar
arch/powerpc/include/asm/disassem
Paul Mackerras writes:
> On Mon, May 05, 2014 at 08:17:00PM +0530, Aneesh Kumar K.V wrote:
>> Alexander Graf writes:
>>
>> > On 05/04/2014 07:30 PM, Aneesh Kumar K.V wrote:
>> >> Signed-off-by: Aneesh Kumar K.V
>> >
>> > No patch descrip
Alexander Graf writes:
> On 05/04/2014 07:30 PM, Aneesh Kumar K.V wrote:
>> Signed-off-by: Aneesh Kumar K.V
>> static inline unsigned long hpte_page_size(unsigned long h, unsigned long
>> l)
>> {
>> +int size, a_size;
>
Alexander Graf writes:
> On 06.05.14 09:19, Benjamin Herrenschmidt wrote:
>> On Tue, 2014-05-06 at 09:05 +0200, Alexander Graf wrote:
>>> On 06.05.14 02:06, Benjamin Herrenschmidt wrote:
On Mon, 2014-05-05 at 17:16 +0200, Alexander Graf wrote:
> Isn't this a greater problem? We should st
Alexander Graf writes:
> On 06.05.14 02:41, Paul Mackerras wrote:
>> On Mon, May 05, 2014 at 01:19:30PM +0200, Alexander Graf wrote:
>>> On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
>>>> +#ifdef CONFIG_PPC_BOOK3S_64
>>>> + return vcpu->arch.faul
Alexander Graf writes:
> On 06.05.14 02:41, Paul Mackerras wrote:
>> On Mon, May 05, 2014 at 01:19:30PM +0200, Alexander Graf wrote:
>>> On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
>>>> +#ifdef CONFIG_PPC_BOOK3S_64
>>>> + return vcpu->arch.faul
Alexander Graf writes:
>> Am 05.05.2014 um 16:35 schrieb "Aneesh Kumar K.V"
>> :
>>
>> Alexander Graf writes:
>>
>>>> On 05/04/2014 07:25 PM, Aneesh Kumar K.V wrote:
>>>> We reserve 5% of total ram for CMA allocation and not
Olof Johansson writes:
> 2014-05-05 7:43 GMT-07:00 Alexander Graf :
>
>> On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
>>
>>> Alexander Graf writes:
>>>
>>> On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
>>>>
>>>&g
Alexander Graf writes:
> On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
>> Alexander Graf writes:
>>
>>> On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
>>>> Although it's optional IBM POWER cpus always had DAR value set on
>>>> alig
Alexander Graf writes:
> On 05/05/2014 04:38 PM, Aneesh Kumar K.V wrote:
>> Alexander Graf writes:
>>
>>> On 05/04/2014 06:36 PM, Aneesh Kumar K.V wrote:
>>>> Alexander Graf writes:
>>>>
>>>>> When running on a POWER8 host, we get
Alexander Graf writes:
> On 05/04/2014 07:30 PM, Aneesh Kumar K.V wrote:
>> Signed-off-by: Aneesh Kumar K.V
>
> No patch description, no proper explanations anywhere why you're doing
> what. All of that in a pretty sensitive piece of code. There's no way
> th
Alexander Graf writes:
> On 05/04/2014 06:36 PM, Aneesh Kumar K.V wrote:
>> Alexander Graf writes:
>>
>>> When running on a POWER8 host, we get away with running the guest as POWER7
>>> and nothing falls apart.
>>>
>>> However, when we start ex
Alexander Graf writes:
> On 05/04/2014 07:25 PM, Aneesh Kumar K.V wrote:
>> We reserve 5% of total ram for CMA allocation and not using that can
>> result in us running out of numa node memory with specific
>> configuration. One caveat is we may not have node local hp
Alexander Graf writes:
> On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
>> Although it's optional IBM POWER cpus always had DAR value set on
>> alignment interrupt. So don't try to compute these values.
>>
>> Signed-off-by: Aneesh Kumar K.V
>>
This patch make sure we inherit the LE bit correctly in different case
so that we can run Little Endian distro in PR mode
Signed-off-by: Aneesh Kumar K.V
---
Changes from V4:
* Don't check for MSR_LE bit while setting LPCR.
arch/powerpc/include/asm/kvm_host.h | 2 +-
arch/powerpc/kerne
"Aneesh Kumar K.V" writes:
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/include/asm/kvm_book3s_64.h | 146
> ++-
> arch/powerpc/kvm/book3s_hv.c | 7 ++
> 2 files changed, 130 insertions(+), 23 deletions(-)
&
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s_64.h | 146 ++-
arch/powerpc/kvm/book3s_hv.c | 7 ++
2 files changed, 130 insertions(+), 23 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_book3s_64.h
b/arch/powerpc
00ec59fd90] [c0225148] .SyS_ioctl+0x58/0xb0
[c000ec59fe30] [c000a1e4] syscall_exit+0x0/0x98
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_pr.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index c5
table.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_64_mmu_hv.c | 23 ++-
1 file changed, 6 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c
b/arch/powerpc/kvm/book3s_64_mmu_hv.c
index fb25ebc0af0c..f32896ffd784 100644
--- a/arch
Although it's optional IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V
---
Changes from V3:
* Use make_dsisr instead of checking feature flag to decide whether to use
saved dsisr or not
arch/power
This patch make sure we inherit the LE bit correctly in different case
so that we can run Little Endian distro in PR mode
Signed-off-by: Aneesh Kumar K.V
---
Changes from V3:
* Address review comments.
* rebase to new kernel so that intr_msr is moved instead of adding a new
variable
* Drop
Alexander Graf writes:
> When running on a POWER8 host, we get away with running the guest as POWER7
> and nothing falls apart.
>
> However, when we start exposing POWER8 as guest CPU, guests will start using
> new abilities on POWER8 which we need to handle.
>
> This patch set does a minimalisti
Alexander Graf writes:
> On 03.04.14 04:36, Liu ping fan wrote:
>> Hi Alex, could you help to pick up this patch? since v3.14 kernel can
>> enable numa fault for powerpc.
>
> What bad happens without this patch? We map a page even though it was
> declared to get NUMA migrated? What happens next
>
> This fixes running book3s_32 kvm as a module for me.
>
> Signed-off-by: Alexander Graf
I thought Greg Kurz had sent a patch for this. Remember discussing this
on irc.
Reviewed-by: Aneesh Kumar K.V
> ---
> arch/powerpc/kvm/book3s.c| 6 +++---
> arch/powerpc/kvm/boo
Paul Mackerras writes:
> On Thu, Mar 06, 2014 at 04:06:09PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V"
>>
>> This reverts commit 7b490411c37f7ab7965cbdfe5e3ec28eadb6db5b which cause
>> the below crash in the host.
>>
>> U
f-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index 557a47800ca1..6962d38c76f5 100644
--- a/arch/p
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