Hi Gleb,
Thanks for the quick reply. Please see below.
On 06/18/2014 02:12 PM, Gleb Natapov wrote:
On Wed, Jun 18, 2014 at 01:50:00PM +0800, Tang Chen wrote:
[Questions]
And by the way, would you guys please answer the following questions for me ?
1. What's the ept identity pagetable for ? O
On Wed, Jun 18, 2014 at 01:50:00PM +0800, Tang Chen wrote:
> [Questions]
> And by the way, would you guys please answer the following questions for me ?
>
> 1. What's the ept identity pagetable for ? Only one page is enough ?
>
> 2. Is the ept identity pagetable only used in realmode ?
>Can
Hi,
I met a problem when offlining memory with a kvm guest running.
[Problem]
When qemu creates vpus, it will call the following two functions
to allocate two pages:
1. alloc_apic_access_page(): allocate apic access page for FlexPriority in
intel cpu.
2. alloc_identity_pagetable(): allocate ept
Check for required-0 or required-1 bits as well as known field value
restrictions. Also check the consistency between VMX_*_CTLS and
VMX_TRUE_*_CTLS and between CR0/4_FIXED0 and CR0/4_FIXED1.
Signed-off-by: Jan Kiszka
---
Changes in v3:
- integrated suggestions of Paolo
x86/vmx.c | 74
On 18.06.14 03:37, Michael Ellerman wrote:
On Wed, 2014-06-18 at 02:59 +0200, Alexander Graf wrote:
On 18.06.14 02:50, Michael Ellerman wrote:
On Tue, 2014-06-17 at 10:27 +0200, Alexander Graf wrote:
On 17.06.14 09:54, Michael Ellerman wrote:
Add support for powerpc platforms. We use uname -
On 06/11/2014 12:03 AM, Christoffer Dall wrote:
>>
>> There is also the issue of kvm_flush_remote_tlbs(), that's also weak,
>> the generic one is using IPIs. Since it's only used in mmu.c maybe make
>> this one static.
>>
> So I don't see a lot of use of weak symbols in kvm_main.c (actually on
>
On Wed, 2014-06-18 at 02:59 +0200, Alexander Graf wrote:
> On 18.06.14 02:50, Michael Ellerman wrote:
> > On Tue, 2014-06-17 at 10:27 +0200, Alexander Graf wrote:
> >> On 17.06.14 09:54, Michael Ellerman wrote:
> >>> Add support for powerpc platforms. We use uname -m, which allows us to
> >>> detec
On 18.06.14 02:50, Michael Ellerman wrote:
On Tue, 2014-06-17 at 10:27 +0200, Alexander Graf wrote:
On 17.06.14 09:54, Michael Ellerman wrote:
Add support for powerpc platforms. We use uname -m, which allows us to
detect ppc, ppc64 and ppc64le/el.
Signed-off-by: Michael Ellerman
Could you p
On Tue, 2014-06-17 at 10:27 +0200, Alexander Graf wrote:
> On 17.06.14 09:54, Michael Ellerman wrote:
> > Add support for powerpc platforms. We use uname -m, which allows us to
> > detect ppc, ppc64 and ppc64le/el.
> >
> > Signed-off-by: Michael Ellerman
>
> Could you please add support for PR KV
On Jun 17, 2014 6:25 PM, Waiman Long wrote:
>
> On 06/17/2014 05:10 PM, Konrad Rzeszutek Wilk wrote:
> > On Tue, Jun 17, 2014 at 05:07:29PM -0400, Konrad Rzeszutek Wilk wrote:
> >> On Tue, Jun 17, 2014 at 04:51:57PM -0400, Waiman Long wrote:
> >>> On 06/17/2014 04:36 PM, Konrad Rzeszutek Wilk
On 06/17/2014 05:10 PM, Konrad Rzeszutek Wilk wrote:
On Tue, Jun 17, 2014 at 05:07:29PM -0400, Konrad Rzeszutek Wilk wrote:
On Tue, Jun 17, 2014 at 04:51:57PM -0400, Waiman Long wrote:
On 06/17/2014 04:36 PM, Konrad Rzeszutek Wilk wrote:
On Sun, Jun 15, 2014 at 02:47:00PM +0200, Peter Zijlstra
Add MAINTAINERS entry for MIPS KVM.
Signed-off-by: James Hogan
---
Changes in v4:
- Add MAINTAINERS entry for MIPS KVM.
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 51a6f51842be..0a637c90c679 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
From: Sanjay Lal
Add API for converting physical addresses to KVM guest KSEG0 addresses,
and fix the existing API for converting KSEG0 addresses to physical
addresses to work in the KVM case. Both have the same sized KSEG0, so
it's just a case of fixing the mask.
In KVM trap and emulate mode bot
From: Sanjay Lal
Compare/Count timer interrupts are handled in-kernel for KVM. Therefore
don't bother creating the timer at init time if KVM is enabled. This
will conveniently avoid attempts to set the timeout when
cpu_mips_store_count() is called at reset with KVM enabled, treating the
timer as
The MIPS CPU timer (CP0 Count/Compare registers & QEMU timer) is
reset at machine initialisation, including starting the timeout. Both
registers however are placed before mvp in CPUMIPSState so they will
both be zeroed on reset by the memset in mips_cpu_reset() including soon
after init. This doesn
From: Sanjay Lal
Implement the main KVM arch API for MIPS.
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Gleb Natapov
Cc: Paolo Bonzini
Cc: Andreas Färber
Cc: Peter Maydell
---
Changes in v5:
- Rename kvm_arch_reset_vcpu to kvm_mips_reset_vcpu based on commi
In KVM mode the bootrom is loaded and executed from the last 1MB of
DRAM.
Based on "[PATCH 12/12] KVM/MIPS: General KVM support and support for
SMP Guests" by Sanjay Lal .
Signed-off-by: James Hogan
Reviewed-by: Aurelien Jarno
Cc: Peter Maydell
Cc: Sanjay Lal
---
Changes in v5:
- Kseg0 doesn
Add preprocessor definitions for 32bit segment bases for use in
get_physical_address(). These will also be taken advantage of in the
next patch which adds KVM awareness.
Signed-off-by: James Hogan
Reviewed-by: Aurelien Jarno
---
target-mips/helper.c | 18 --
1 file changed, 12 i
From: Sanjay Lal
Enable KVM support for MIPS in the build system.
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Reviewed-by: Aurelien Jarno
---
Changes in v2:
- Expand commit message
- Remove GIC code
- Create asm-mips symlink using generic code and move above default
case (Peter
The patchset depends on v4 of "target-mips: implement UserLocal
Register". I'm aiming for QEMU 2.1, hopefully it isn't too late to get
some final review.
Thanks to everybody who has already taken part in review.
This patchset implements KVM support for MIPS32 processors, using Trap &
Emulation.
MIPS KVM trap & emulate mode (which is currently the only supported
mode) has to add an extra kseg0/kseg1 at 0x4000 and an extra
kseg2/kseg3 at 0x6000. Take this into account in
get_physical_address() so that debug memory access works.
This is done by translating the address to a standard
When KVM is enabled call kvm_mips_reset_vcpu() from mips_cpu_reset() as
done for other targets since commit 50a2c6e55fa2 (kvm: reset state from
the CPU's reset method).
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Paolo Bonzini
Cc: Gleb Natapov
---
Changes in v5:
- New patch, based on co
From: Sanjay Lal
COP0 emulation is in-kernel for KVM, so inject IRQ2 (I/O) interrupts via
ioctls.
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Reviewed-by: Aurelien Jarno
Reviewed-by: Andreas Färber
---
Changes in v5:
- Fix typo in subject (s/interupts/interrupts/)
Changes in v3:
MIPS/Linux is unusual in having 128 signals rather than just 64 like
most other architectures. This means its sigmask is 16 bytes instead of
8, so allow arches to override the sigmask->len value passed to the
KVM_SET_SIGNAL_MASK ioctl in kvm_set_signal_mask() by calling
kvm_set_sigmask_len() from k
On Tue, Jun 17, 2014 at 04:51:57PM -0400, Waiman Long wrote:
> On 06/17/2014 04:36 PM, Konrad Rzeszutek Wilk wrote:
> >On Sun, Jun 15, 2014 at 02:47:00PM +0200, Peter Zijlstra wrote:
> >>Because the qspinlock needs to touch a second cacheline; add a pending
> >>bit and allow a single in-word spinne
On Sun, Jun 15, 2014 at 03:16:54PM +0200, Peter Zijlstra wrote:
> On Thu, Jun 12, 2014 at 04:48:41PM -0400, Waiman Long wrote:
> > I don't have a good understanding of the kernel alternatives mechanism.
>
> I didn't either; I do now, cost me a whole day reading up on
> alternative/paravirt code pa
On Tue, Jun 17, 2014 at 05:07:29PM -0400, Konrad Rzeszutek Wilk wrote:
> On Tue, Jun 17, 2014 at 04:51:57PM -0400, Waiman Long wrote:
> > On 06/17/2014 04:36 PM, Konrad Rzeszutek Wilk wrote:
> > >On Sun, Jun 15, 2014 at 02:47:00PM +0200, Peter Zijlstra wrote:
> > >>Because the qspinlock needs to to
On Sun, Jun 15, 2014 at 02:47:01PM +0200, Peter Zijlstra wrote:
> From: Waiman Long
>
> This patch extracts the logic for the exchange of new and previous tail
> code words into a new xchg_tail() function which can be optimized in a
> later patch.
And also adds a third try on acquiring the lock.
On 06/17/2014 04:36 PM, Konrad Rzeszutek Wilk wrote:
On Sun, Jun 15, 2014 at 02:47:00PM +0200, Peter Zijlstra wrote:
Because the qspinlock needs to touch a second cacheline; add a pending
bit and allow a single in-word spinner before we punt to the second
cacheline.
Could you add this in the de
On 17.06.14 22:36, mihai.cara...@freescale.com wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, June 17, 2014 11:05 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org
Subject: Re: [PATCH v3] KVM: PPC: e500
On Sun, Jun 15, 2014 at 02:47:00PM +0200, Peter Zijlstra wrote:
> Because the qspinlock needs to touch a second cacheline; add a pending
> bit and allow a single in-word spinner before we punt to the second
> cacheline.
Could you add this in the description please:
And by second cacheline we mean
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, June 17, 2014 11:05 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: [PATCH v3] KVM: PPC: e500mc: Enhance tlb invalidation
> condition on
> + * The basic principle of a queue-based spinlock can best be understood
> + * by studying a classic queue-based spinlock implementation called the
> + * MCS lock. The paper below provides a good description for this kind
> + * of lock.
> + *
> + * http://www.cise.ufl.edu/tr/DOC/REP-1992-71.pdf
>
On Tue, 2014-06-17 at 15:02 -0500, Caraman Mihai Claudiu-B02008 wrote:
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: Tuesday, June 17, 2014 10:48 PM
> > To: Caraman Mihai Claudiu-B02008
> > Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> > d...@lists.ozlabs.org
> > + new = tail | (val & _Q_LOCKED_MASK);
> > +
> > + old = atomic_cmpxchg(&lock->val, val, new);
> > + if (old == val)
> > + break;
> > +
> > + val = old;
> > + }
> > +
> > + /*
> > +* we won the trylock; forget about queue
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, June 17, 2014 10:48 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: [PATCH v3] KVM: PPC: e500mc: Enhance tlb invalidation
> condition on
On Tue, 2014-06-17 at 14:42 -0500, Caraman Mihai Claudiu-B02008 wrote:
> > > -static DEFINE_PER_CPU(struct kvm_vcpu *, last_vcpu_on_cpu);
> > > +static DEFINE_PER_CPU(struct kvm_vcpu * [KVMPPC_NR_LPIDS],
> > last_vcpu_on_cpu);
> >
> > Hmm, I didn't know you could express types like that. Is this
> > -static DEFINE_PER_CPU(struct kvm_vcpu *, last_vcpu_on_cpu);
> > +static DEFINE_PER_CPU(struct kvm_vcpu * [KVMPPC_NR_LPIDS],
> last_vcpu_on_cpu);
>
> Hmm, I didn't know you could express types like that. Is this special
> syntax that only works for typeof?
Yes, AFAIK.
> No space after *
Ch
On Tue, 2014-06-17 at 22:09 +0300, Mihai Caraman wrote:
> On vcpu schedule, the condition checked for tlb pollution is too loose.
> The tlb entries of a vcpu become polluted (vs stale) only when a different
> vcpu within the same logical partition runs in-between. Optimize the tlb
> invalidation co
On vcpu schedule, the condition checked for tlb pollution is too loose.
The tlb entries of a vcpu become polluted (vs stale) only when a different
vcpu within the same logical partition runs in-between. Optimize the tlb
invalidation condition keeping last_vcpu_on_cpu per logical partition id.
With
On Tue, 2014-06-17 at 14:04 -0500, Caraman Mihai Claudiu-B02008 wrote:
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: Tuesday, June 17, 2014 6:36 PM
> > To: Caraman Mihai Claudiu-B02008
> > Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> > d...@lists.ozlabs.org
>
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, June 17, 2014 6:36 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: [PATCH v2] KVM: PPC: e500mc: Enhance tlb invalidation
> condition on
Il 17/04/2014 16:17, Andrew Jones ha scritto:
Signed-off-by: Andrew Jones
---
x86/unittests.cfg | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/x86/unittests.cfg b/x86/unittests.cfg
index 7930c026a38d6..d78fe0eafe2b6 100644
--- a/x86/unittests.cfg
+++ b/x86/unittests.cfg
@@
Il 17/06/2014 16:36, Andrew Jones ha scritto:
Add report_xfail(), which is report(), but with another condition
allowing it to output PASS/FAIL/XPASS/XFAIL, rather than only
PASS/FAIL. This allows report output to stay more consistent
between systems/configurations that may or may not support all
From: Nikolay Nikolaev
Add a function to check if the eventfd capability is present in KVM in
the host kernel.
Signed-off-by: Antonios Motakis
Signed-off-by: Nikolay Nikolaev
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
Acked-by: Paolo Bonzini
---
include/sysemu/kvm.h
On Jun 17, 2014, at 12:05 AM, Gleb Natapov wrote:
> On Tue, Jun 17, 2014 at 06:21:23AM +0200, Paolo Bonzini wrote:
>> Il 16/06/2014 18:47, John Nielsen ha scritto:
>>> On Jun 16, 2014, at 10:39 AM, Paolo Bonzini wrote:
>>>
Il 16/06/2014 18:09, John Nielsen ha scritto:
>>> The only subs
Il 17/06/2014 17:35, Bandan Das ha scritto:
Well, I meant it more as a review and "suggested changes" to this patchset
Nadav posted, but yeah, if you prefer, I can post a change myself. I will
make a pass through other uses of BUG() in the code too.
I'd prefer that, there's no need to make Nada
So far we've been able to successfully run HV KVM on big endian hosts, but
once you dive into little endian land things start to fall apart.
This patch set enables HV KVM for little endian hosts. This should be the
final piece left missing to get little endian systems fully en par with big
endian
We use ABIv2 on Little Endian systems which gets rid of the dotted function
names. Branch to the actual functions when we see such a system.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
di
On the exit path from the guest we check what type of interrupt we received
if we received one. This means we're doing hardware access to the XICS interrupt
controller.
However, when running on a little endian system, this access is byte reversed.
So let's make sure to swizzle the bytes back agai
>From assembly code we might not only have to explicitly BE access 64bit values,
but sometimes also 32bit ones. Add helpers that allow for easy use of lwzx/stwx
in their respective byte-reverse or native form.
Signed-off-by: Alexander Graf
CC: Benjamin Herrenschmidt
---
v1 -> v2:
- fix typo
There are a few shared data structures between the host and the guest. Most
of them get registered through the VPA interface.
These data structures are defined to always be in big endian byte order, so
let's make sure we always access them in big endian.
Signed-off-by: Alexander Graf
---
v1 ->
Now that we've fixed all the issues that HV KVM code had on little endian
hosts, we can enable it in the kernel configuration for users to play with.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/kvm/Kconfig b/arch/powe
Some data structures are always stored in big endian. Among those are the LPPACA
fields as well as the shadow slb. These structures might be shared with a
hypervisor.
So whenever we access those fields, make sure we do so in big endian byte order.
Signed-off-by: Alexander Graf
---
arch/powerpc/
When running on an LE host all data structures are kept in little endian
byte order. However, the HTAB still needs to be maintained in big endian.
So every time we access any HTAB we need to make sure we do so in the right
byte order. Fix up all accesses to manually byte swap.
Signed-off-by: Alex
We switched to ABIv2 on Little Endian systems now which gets rid of the
dotted function names. Branch to the actual functions when we see such
a system.
Signed-off-by: Alexander Graf
diff --git a/arch/powerpc/kvm/book3s_interrupts.S
b/arch/powerpc/kvm/book3s_interrupts.S
index e2c29e3..d044b8b
On 12.06.14 10:16, Anton Blanchard wrote:
Both kvmppc_hv_entry_trampoline and kvmppc_entry_trampoline are
assembly functions that are exported to modules and also require
a valid r2.
As such we need to use _GLOBAL_TOC so we provide a global entry
point that establishes the TOC (r2).
Signed-off
On 12.06.14 10:16, Anton Blanchard wrote:
To establish addressability quickly, ABIv2 requires the target
address of the function being called to be in r12.
Signed-off-by: Anton Blanchard
Thanks, applied to kvm-ppc-queue.
Alex
---
Index: b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
If we're running PR KVM in HV mode, we may get hypervisor doorbell interrupts.
Handle those the same way we treat normal doorbells.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_pr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/b
Paolo Bonzini writes:
> Il 16/06/2014 19:38, Bandan Das ha scritto:
>> Nadav Amit writes:
>>
>>> The emulator does not emulate the xadd instruction correctly if the two
>>> operands are the same. In this (unlikely) situation the result should be
>>> the
>>> sum of X and X (2X) when it is curre
On Thu, 2014-06-12 at 19:04 +0200, Alexander Graf wrote:
> On 06/12/2014 04:00 PM, Mihai Caraman wrote:
> > @@ -140,12 +142,24 @@ static void kvmppc_core_vcpu_load_e500mc(struct
> > kvm_vcpu *vcpu, int cpu)
> > mtspr(SPRN_GDEAR, vcpu->arch.shared->dar);
> > mtspr(SPRN_GESR, vcpu->arch.shar
On Tue, 2014-06-17 at 12:02 +0300, Mihai Caraman wrote:
> On vcpu schedule, the condition checked for tlb pollution is too loose.
> The tlb entries of a vcpu become polluted (vs stale) only when a different
> vcpu within the same logical partition runs in-between. Optimize the tlb
> invalidation co
On 17.06.14 13:13, Madhavan Srinivasan wrote:
On Tuesday 17 June 2014 04:38 PM, Alexander Graf wrote:
On 17.06.14 13:07, Madhavan Srinivasan wrote:
On Tuesday 17 June 2014 02:24 PM, Alexander Graf wrote:
On 14.06.14 23:08, Madhavan Srinivasan wrote:
This patch adds kernel side support for so
Add report_xfail(), which is report(), but with another condition
allowing it to output PASS/FAIL/XPASS/XFAIL, rather than only
PASS/FAIL. This allows report output to stay more consistent
between systems/configurations that may or may not support all
tests.
Signed-off-by: Andrew Jones
---
lib/l
On Tue, Jun 17, 2014 at 02:46:30PM +0200, Paolo Bonzini wrote:
> Il 17/06/2014 14:21, Andrew Jones ha scritto:
> >would look better as
> >
> >report(msg1, cond1) -> FAIL
> >report_skip(msg2, !cond1, cond1 && cond2) -> SKIP
> >report_skip(msg3, !cond1, cond1 && cond3)
Il 17/06/2014 14:21, Andrew Jones ha scritto:
would look better as
report(msg1, cond1) -> FAIL
report_skip(msg2, !cond1, cond1 && cond2) -> SKIP
report_skip(msg3, !cond1, cond1 && cond3) -> SKIP
I think a lot of the time there is other code before the report t
Add report_skip(), which is report(), but with another condition
allowing it to output PASS/FAIL/SKIP, rather than only PASS/FAIL.
This allows report output to stay more consistent between
systems/configurations that may or may not support all tests.
Currently I only have a downstream use case for
On 17.06.14 14:13, Paul Mackerras wrote:
On Tue, Jun 17, 2014 at 12:22:32PM +0200, Alexander Graf wrote:
Eh, no. What we do is we read (good on BE, byte reversed) into r0. Then we
swab32() from r0 to r3 on LE, mr from r0 to r3 on BE.
r3 gets truncated along the way.
The reason we maintain r0
On Tue, Jun 17, 2014 at 12:22:32PM +0200, Alexander Graf wrote:
>
> Eh, no. What we do is we read (good on BE, byte reversed) into r0. Then we
> swab32() from r0 to r3 on LE, mr from r0 to r3 on BE.
>
> r3 gets truncated along the way.
>
> The reason we maintain r0 as wrong-endian is that we wri
Juan Quintela wrote:
> Hi
I sent the first mail to the wrong address, please notice that
qemu-devel was missing). Fixed in this resent.
Sorry for the inconveniences.
Later, Juan.
> Please, send any topic that you are interested in covering.
>
> * Machine as QOM (Marcel) (repeat)
> - Solve th
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Tuesday, June 17, 2014 12:09 PM
> To: Wood Scott-B07421
> Cc: Caraman Mihai Claudiu-B02008; kvm-...@vger.kernel.org;
> kvm@vger.kernel.org; linuxppc-...@lists.ozlabs.org
> Subject: Re: [PATCH] KVM: PPC: e500mc: Relax
On Thu, Apr 17, 2014 at 04:17:42PM +0200, Andrew Jones wrote:
> Signed-off-by: Andrew Jones
> ---
> x86/unittests.cfg | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/x86/unittests.cfg b/x86/unittests.cfg
> index 7930c026a38d6..d78fe0eafe2b6 100644
> --- a/x86/unittests.c
On 06/06/2014 02:16 PM, Christoffer Dall wrote:
> On Mon, Jun 02, 2014 at 02:54:12PM +0100, Marc Zyngier wrote:
>> Hi Eric,
>>
>> On Mon, Jun 02 2014 at 8:29:56 am BST, Eric Auger
>> wrote:
>>> This patch enables irqfd and irq routing on ARM.
>>>
>>> It turns on CONFIG_HAVE_KVM_EVENTFD and CONFI
Hello,
I have a question related to KVM_IRQFD and KVM_SET_GSI_ROUTING ioctl
relationship.
When reading the KVM API documentation I do not understand there is any
dependency between KVM_IRQFD and KVM_SET_GSI_ROUTING. According to the
text it seems only the gsi field is used and interpreted as the
On 17.06.14 13:20, Madhavan Srinivasan wrote:
On Tuesday 17 June 2014 03:13 PM, Alexander Graf wrote:
On 17.06.14 11:32, Benjamin Herrenschmidt wrote:
On Tue, 2014-06-17 at 11:25 +0200, Alexander Graf wrote:
On 17.06.14 11:22, Benjamin Herrenschmidt wrote:
On Tue, 2014-06-17 at 10:54 +0200,
Hi
Please, send any topic that you are interested in covering.
* Machine as QOM (Marcel) (repeat)
- Solve the 'sensible' issues.
- Choose as first tasks the ones that will be more useful.
- Select solutions agreed by everyone.
Thanks, Juan.
Call details:
15:00 CEST
13:00 UTC
09:00 EDT
Ev
On Tuesday 17 June 2014 03:13 PM, Alexander Graf wrote:
>
> On 17.06.14 11:32, Benjamin Herrenschmidt wrote:
>> On Tue, 2014-06-17 at 11:25 +0200, Alexander Graf wrote:
>>> On 17.06.14 11:22, Benjamin Herrenschmidt wrote:
On Tue, 2014-06-17 at 10:54 +0200, Alexander Graf wrote:
> Also, wh
On Tuesday 17 June 2014 04:38 PM, Alexander Graf wrote:
>
> On 17.06.14 13:07, Madhavan Srinivasan wrote:
>> On Tuesday 17 June 2014 02:24 PM, Alexander Graf wrote:
>>> On 14.06.14 23:08, Madhavan Srinivasan wrote:
This patch adds kernel side support for software breakpoint.
Design is th
On Tuesday 17 June 2014 03:02 PM, Benjamin Herrenschmidt wrote:
> On Tue, 2014-06-17 at 11:25 +0200, Alexander Graf wrote:
>> On 17.06.14 11:22, Benjamin Herrenschmidt wrote:
>>> On Tue, 2014-06-17 at 10:54 +0200, Alexander Graf wrote:
Also, why don't we use twi always or something else that a
On 17.06.14 13:07, Madhavan Srinivasan wrote:
On Tuesday 17 June 2014 02:24 PM, Alexander Graf wrote:
On 14.06.14 23:08, Madhavan Srinivasan wrote:
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation
On Tuesday 17 June 2014 02:24 PM, Alexander Graf wrote:
>
> On 14.06.14 23:08, Madhavan Srinivasan wrote:
>> This patch adds kernel side support for software breakpoint.
>> Design is that, by using an illegal instruction, we trap to hypervisor
>> via Emulation Assistance interrupt, where we check
I see kernel 3.15 is now out, so I retested with 3.15 guest and host. I'm
still getting exactly the same guest kernel panic: a divide error in
kvm_unlock_kick with -cpu host, but not with -cpu qemu64:
divide error: [#1] PREEMPT SMP
Modules linked in:
CPU: 1 PID: 781 Comm: mkdir Not tainted 3
On 17.06.14 10:37, Alexander Graf wrote:
On 17.06.14 03:02, Paul Mackerras wrote:
On Wed, Jun 11, 2014 at 12:33:50PM +0200, Alexander Graf wrote:
On the exit path from the guest we check what type of interrupt we
received
if we received one. This means we're doing hardware access to the
XICS
On Tue, Jun 17, 2014 at 12:03:58PM +0200, Alexander Graf wrote:
> When we're using PR KVM we must not allow the CPU to take interrupts
> in virtual mode, as the SLB does not contain host kernel mappings
> when running inside the guest context.
>
> To make sure we get good performance for non-KVM t
When we're using PR KVM we must not allow the CPU to take interrupts
in virtual mode, as the SLB does not contain host kernel mappings
when running inside the guest context.
To make sure we get good performance for non-KVM tasks but still
properly functioning PR KVM, let's just disable AIL wheneve
Il 17/06/2014 11:03, David Marchand ha scritto:
Unless someone steps up and maintains ivshmem, I think it should be
deprecated and dropped from QEMU.
Then I can maintain ivshmem for QEMU.
If this is ok, I will send a patch for MAINTAINERS file.
Typically, adding yourself to maintainers is don
On 17.06.14 11:32, Benjamin Herrenschmidt wrote:
On Tue, 2014-06-17 at 11:25 +0200, Alexander Graf wrote:
On 17.06.14 11:22, Benjamin Herrenschmidt wrote:
On Tue, 2014-06-17 at 10:54 +0200, Alexander Graf wrote:
Also, why don't we use twi always or something else that actually is
defined as i
On Tue, 2014-06-17 at 11:25 +0200, Alexander Graf wrote:
> On 17.06.14 11:22, Benjamin Herrenschmidt wrote:
> > On Tue, 2014-06-17 at 10:54 +0200, Alexander Graf wrote:
> >> Also, why don't we use twi always or something else that actually is
> >> defined as illegal instruction? I would like to see
On 17.06.14 11:22, Benjamin Herrenschmidt wrote:
On Tue, 2014-06-17 at 10:54 +0200, Alexander Graf wrote:
Also, why don't we use twi always or something else that actually is
defined as illegal instruction? I would like to see this shared with
book3s_32 PR.
twi will be directed to the guest on
On Tue, 2014-06-17 at 10:54 +0200, Alexander Graf wrote:
>
> Also, why don't we use twi always or something else that actually is
> defined as illegal instruction? I would like to see this shared with
> book3s_32 PR.
twi will be directed to the guest on HV no ? We want a real illegal
because th
On 12.06.14 05:56, Paul Mackerras wrote:
On Tue, Jun 10, 2014 at 07:23:00PM +0200, Alexander Graf wrote:
When we're using PR KVM we must not allow the CPU to take interrupts
in virtual mode, as the SLB does not contain host kernel mappings
when running inside the guest context.
To make sure we
On 13.06.14 21:42, Scott Wood wrote:
On Fri, 2014-06-13 at 16:55 +0200, Alexander Graf wrote:
On 13.06.14 16:43, mihai.cara...@freescale.com wrote:
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Thursday, June 12, 2014 8:05 PM
To: Caraman Mihai Claudiu-B02008
Cc:
On Thu, Jun 12, 2014 at 06:48:14PM +0200, urgrue wrote:
> Does anyone have ANY idea where I could find out about market share and
> adoption rates of linux hypervisors (kvm vs xen vs vmware, mainly)?
> I've not found anything despite extensive searching, which is really kind of
> problematic when y
Hello all,
On 06/17/2014 04:54 AM, Stefan Hajnoczi wrote:
ivshmem has a performance disadvantage for guest-to-host
communication. Since the shared memory is exposed as PCI BARs, the
guest has to memcpy into the shared memory.
vhost-user can access guest memory directly and avoid the copy insid
On vcpu schedule, the condition checked for tlb pollution is too loose.
The tlb entries of a vcpu become polluted (vs stale) only when a different
vcpu within the same logical partition runs in-between. Optimize the tlb
invalidation condition taking into account the logical partition id.
With the
On 14.06.14 23:08, Madhavan Srinivasan wrote:
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation Assistance interrupt, where we check for the illegal instruction
and accordingly we return to Host or Gu
On 17.06.14 03:02, Paul Mackerras wrote:
On Wed, Jun 11, 2014 at 12:33:50PM +0200, Alexander Graf wrote:
On the exit path from the guest we check what type of interrupt we received
if we received one. This means we're doing hardware access to the XICS interrupt
controller.
However, when runnin
On 17.06.14 02:51, Paul Mackerras wrote:
On Wed, Jun 11, 2014 at 12:33:46PM +0200, Alexander Graf wrote:
>From assembly code we might not only have to explicitly BE access 64bit values,
but sometimes also 32bit ones. Add helpers that allow for easy use of lwzx/stwx
in their respective byte-reve
On 17.06.14 09:54, Michael Ellerman wrote:
Add support for powerpc platforms. We use uname -m, which allows us to
detect ppc, ppc64 and ppc64le/el.
Signed-off-by: Michael Ellerman
Could you please add support for PR KVM tracepoints along the way? There
we do know the exit reason for every s
Il 17/06/2014 09:04, Jan Kiszka ha scritto:
+ default1 = vmx_ctl_msr[n].default1;
+ ok = (ctrl.set & default1) == default1 &&
+ ((ctrl.set ^ ctrl.clr) & ~ctrl.clr) == 0;
Thanks, now I can understand what's going on. :) It can still be
simplifi
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