On 14/11/17 11:50, miles mccoo wrote:
> I do see that the implementation of GetPadCount(aNet) does just that.[3]
> Also, in that implementation, it's referencing connAlgo's padList. Is
> this better than asking board for its pads? I'm thinking the whole
> "don't repeat yourself" thing [4]
Would yo
BOARD_CONNECTED_ITEM::GetNet()?
On 11/14/2017 5:50 AM, miles mccoo wrote:
>
>
> old thread, but I think it's relevant to my issue. My interest is mostly
> in the python interface to pcbnew.[0]
>
>
> With the new connectivity stuff, what's the proper way to ask a net what
> pads belong to it?
>
old thread, but I think it's relevant to my issue. My interest is mostly in
the python interface to pcbnew.[0]
With the new connectivity stuff, what's the proper way to ask a net what
pads belong to it?
In python, I used to be able to do net.Pads() [1]
I tried adding connectivity.h[2] to boards
Hey Tom!
Any ETA for the new Via tool dialog? It's some solid work you have done,
thanks!
- Kristoffer
On 2017-06-27 21:54, Tomasz Wlostowski wrote:
On 27.06.2017 21:24, Simon Küppers wrote:
Small Bump.
Can anyone shed some light on the new Via Tool? Is it supposed to be not
ready yet? The
Hi Orson,
tested with latest commits and now is fine.
thanks a lot
Maurice
On 6/30/2017 9:46 PM, Maciej Suminski wrote:
Hi Maurice,
What revision did you use? Today I fixed it (da051379), so it depends
whether you already have the recent patches. Let me know if there are
still problems.
Rega
Hi Maurice,
What revision did you use? Today I fixed it (da051379), so it depends
whether you already have the recent patches. Let me know if there are
still problems.
Regards,
Orson
On 06/30/2017 05:58 PM, easyw wrote:
> Hi,
> I'm having a strange behavior when loading a netlist
>
> with the m
Hi,
I'm having a strange behavior when loading a netlist
with the menu Tools, Load Netlist
if I select to Delete Single Pads Nets, almost all pads will lose their
connectivity... (you can see in the report that the algo is deleting the
net connectivity when parsing the pads)
This was not the p
On 29.06.2017 18:36, Heikki Pulkkinen wrote:
> Hi
>
> Just start implementing my tools to new connectivity algorithm, and
> noticed that via stitchin chain needs to as many copper pour fills as
> there are chain links. Videos show what I mean.
>
Hi Heikki,
Can you send us the board that you hav
Hi
Just start implementing my tools to new connectivity algorithm, and noticed
that via stitchin chain needs to as many copper pour fills as there are
chain links. Videos show what I mean.
regards
Heikki
new: https://youtu.be/ZV4AMstIdQY
old: https://youtu.be/QGr2p6M6Su0
On Tue, Apr 25, 2017 a
Don't worry! I was just curious.
Best Regards
Simon
Am 27.06.2017 um 21:54 schrieb Tomasz Wlostowski:
> On 27.06.2017 21:24, Simon Küppers wrote:
>> Small Bump.
>>
>> Can anyone shed some light on the new Via Tool? Is it supposed to be not
>> ready yet? The Track & Via Properties Dialog looks rea
On 27.06.2017 21:24, Simon Küppers wrote:
> Small Bump.
>
> Can anyone shed some light on the new Via Tool? Is it supposed to be not
> ready yet? The Track & Via Properties Dialog looks really unfinished and
> I cannot modify anything beside Position and Via Size there. Is it
> because I am using
Small Bump.
Can anyone shed some light on the new Via Tool? Is it supposed to be not
ready yet? The Track & Via Properties Dialog looks really unfinished and
I cannot modify anything beside Position and Via Size there. Is it
because I am using the Cairo Canvas?
Best Regards
Simon
Am 25.06.2017 u
Hi,
This is very nice, especially since I am waiting for it to implement
in my Python Viafence Plugin.
However one thing I don't understand is where can I see the Net
assigned to the Via?
If I place a Via into a Zone and go into Properties, There is a
Combobox to the top left, which is disabled an
On 6/23/2017 4:47 PM, Maciej Suminski wrote:
> On 06/23/2017 08:41 PM, Wayne Stambaugh wrote:
>> On 6/23/2017 1:01 PM, Maciej Sumiński wrote:
> [snip]
>>> While discussing this topic, I suggest also removing unconnected nodes
>>> count and board bounding box, as they are also computed on the fly.
>
On 06/23/2017 08:41 PM, Wayne Stambaugh wrote:
> On 6/23/2017 1:01 PM, Maciej Sumiński wrote:
[snip]
>> While discussing this topic, I suggest also removing unconnected nodes
>> count and board bounding box, as they are also computed on the fly.
>
> I'm not sure the unconnected nodes count should
On 6/23/2017 1:01 PM, Maciej Sumiński wrote:
> Hi,
>
> After a long testing period, it is time to commit the new connectivity
> algorithm. We have neither received any new bug reports, nor we could
> find any defects ourselves.
>
> Effectively it means:
> - long awaited stitching vias are at your
Hi,
After a long testing period, it is time to commit the new connectivity
algorithm. We have neither received any new bug reports, nor we could
find any defects ourselves.
Effectively it means:
- long awaited stitching vias are at your service
- ratsnest calculations should be much faster
- rats
Hi All,
I had perform some speed test on a complex board (12 layers, 42 zones,
649 nets, 2156 pads, 8556 tracks) and as far as I see it's really better:
- Open/close pcbnew test:
=> 24 seconds with current code
=> 8 seconds with this new algo
- Move a single module/footprint:
=> 14 seconds
Hi Tomasz,
any updates about connectivity algorithm?
Jakub
Dne 25.4.2017 v 17:23 Tomasz Wlostowski napsal(a):
Hi all,
I've pushed the branch [1] containing a rewrite of the pcbnew's
connectivity algorithm. By this algorithm, I mean:
- computing the ratsnest and checking if all connections are
And current algo.
https://youtu.be/QSEZkmpLwvc
On Sat, May 20, 2017 at 1:49 PM, Heikki Pulkkinen
wrote:
> Hi Tomasz,
>
> Just tested, sorry to say, that it was hard. Mouse wheel zoom and clicks
> does not work at all.I am using Fedora 24. One notice is, that It is taking
> so much processor tim
2017-04-25 17:23 GMT+02:00 Tomasz Wlostowski :
>
> Hi all,
>
> I've pushed the branch [1] containing a rewrite of the pcbnew's
> connectivity algorithm. By this algorithm, I mean:
> - computing the ratsnest and checking if all connections are complete
> - propagating net codes from the pads to the
Hi,
On 25.04.2017 17:23, Tomasz Wlostowski wrote:
> I've pushed the branch [1] containing a rewrite of the pcbnew's
> connectivity algorithm. By this algorithm, I mean:
There is a new compiler warning:
pcbnew/edit.cpp: In member function 'void
PCB_EDIT_FRAME::OnSelectTool(wxCommandEvent&)':
/ho
On 28.04.2017 23:04, Jakub Kozdon wrote:
> Hi Tom,
>
> Can not build on Linux (LMDE2 3.16.0-4-amd64) see log.
>
> KiCad master build like a charm.
>
Hi Jakub,
Fixed, give it a try if you can...
Cheers,
Tom
> Jakub
>
> Dne 25.4.2017 v 17:23 Tomasz Wlostowski napsal(a):
>> Hi all,
>>
>> I've p
On 28.04.2017 23:04, Jakub Kozdon wrote:
> Hi Tom,
>
> Can not build on Linux (LMDE2 3.16.0-4-amd64) see log.
>
> KiCad master build like a charm.
>
Looks like an issue with Python bindings. Can some Python gurus here
look at this?
Cheers,
Tom
> Jakub
>
> Dne 25.4.2017 v 17:23 Tomasz Wlostow
On 27.04.2017 08:19, jp charras wrote:
> Le 26/04/2017 à 21:53, Tomasz Wlostowski a écrit :
>> On 26.04.2017 21:28, jp charras wrote:
>>> Le 26/04/2017 à 20:54, Tomasz Wlostowski a écrit :
>
> I did not noticed strange things.
> However I ran into an issue when running the DRC:
> th
Le 26/04/2017 à 21:53, Tomasz Wlostowski a écrit :
> On 26.04.2017 21:28, jp charras wrote:
>> Le 26/04/2017 à 20:54, Tomasz Wlostowski a écrit :
I did not noticed strange things.
However I ran into an issue when running the DRC:
the tracks test (clearance test) is very slow:
>>
On 26.04.2017 21:28, jp charras wrote:
> Le 26/04/2017 à 20:54, Tomasz Wlostowski a écrit :
>>>
>>> I did not noticed strange things.
>>> However I ran into an issue when running the DRC:
>>> the tracks test (clearance test) is very slow:
>>> Calculation time is x20 to x25
>>>
Hi JP,
Fixed. Thanks
Le 26/04/2017 à 20:54, Tomasz Wlostowski a écrit :
> On 26.04.2017 20:23, jp charras wrote:
>> Le 25/04/2017 à 17:23, Tomasz Wlostowski a écrit :
>>>
>>> Hi all,
>>>
>>> I've pushed the branch [1] containing a rewrite of the pcbnew's
>>> connectivity algorithm. By this algorithm, I mean:
>>> - comp
On 26.04.2017 20:23, jp charras wrote:
> Le 25/04/2017 à 17:23, Tomasz Wlostowski a écrit :
>>
>> Hi all,
>>
>> I've pushed the branch [1] containing a rewrite of the pcbnew's
>> connectivity algorithm. By this algorithm, I mean:
>> - computing the ratsnest and checking if all connections are compl
Le 25/04/2017 à 17:23, Tomasz Wlostowski a écrit :
>
> Hi all,
>
> I've pushed the branch [1] containing a rewrite of the pcbnew's
> connectivity algorithm. By this algorithm, I mean:
> - computing the ratsnest and checking if all connections are complete
> - propagating net codes from the pads t
Hi all,
I've pushed the branch [1] containing a rewrite of the pcbnew's
connectivity algorithm. By this algorithm, I mean:
- computing the ratsnest and checking if all connections are complete
- propagating net codes from the pads to the tracks/vias
- removing unconnected copper islands in zones
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