As with arm-smmu from whence this code was borrowed, the IOVAs passed in
here happen to be at least page-aligned anyway, but still; oh dear.
Signed-off-by: Robin Murphy
---
drivers/iommu/qcom_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/qcom_iommu.c
Finish the final part of the job, once again updating some names to
match the current spec.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu-regs.h | 86 ++-
drivers/iommu/arm-smmu.c | 16 +++
drivers/iommu/qcom_iommu.c| 13 +++---
3 files
The smmu_write_atomic_lq oddity made some sense when the context
format was effectively tied to CONFIG_64BIT, but these days it's
simpler to just pick an explicit access size based on the format
for the one-and-a-half times we actually care.
Signed-off-by: Robin Murphy
---
drivers/iomm
cb_base into a page number rather than an absolute address.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index a877de006d02..19126230c780
cture spec (IHI0062D.c).
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu-regs.h | 33 ++---
drivers/iommu/arm-smmu.c | 18 +-
2 files changed, 23 insertions(+), 28 deletions(-)
diff --git a/drivers/iommu/arm-smmu-regs.h b/drivers/iommu/arm
conflicts. As somewhat of a template, we'll start with a
general place to collect the relatively trivial existing quirks.
Signed-off-by: Robin Murphy
---
MAINTAINERS | 3 +-
drivers/iommu/Makefile| 2 +-
drivers/iommu/arm-smmu-impl.c | 13 +
drivers/iommu/arm-s
Context bank accesses are fiddly enough to deserve a number of extra
helpers to keep the callsites looking sane, even though there are only
one or two of each.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 138 +--
1 file changed, 73 insertions
Introduce some register access abstractions which we will later use to
encapsulate various quirks. GR1 is the easiest page to start with.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 34 +++---
1 file changed, 27 insertions(+), 7 deletions(-)
diff
We're about to start using it for more than just register definitions,
so generalise the name.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 2 +-
drivers/iommu/{arm-smmu-regs.h => arm-smmu.h} | 6 +++---
drivers/iommu/qcom_iommu.c|
Since we now use separate iommu_gather_ops for stage 1 and stage 2
contexts, we may as well divide up the monolithic callback into its
respective stage 1 and stage 2 parts.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 66 ++--
1 file changed, 37
Probing the ID registers and setting up the SMMU configuration is an
area where overrides and workarounds may well be needed. Indeed, the
Cavium workaround detection lives there at the moment, so let's break
that out.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu-impl.c
Reset is an activity rife with implementation-defined poking. Add a
corresponding hook, and use it to encapsulate the existing MMU-500
details.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu-impl.c | 49 +++
drivers/iommu/arm-smmu.c | 39
Allocating and initialising a context for a domain is another point
where certain implementations are known to want special behaviour.
Currently the other half of the Cavium workaround comes into play here,
so let's finish the job to get the whole thing right out of the way.
Signed-off-by:
machinery.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu-impl.c | 44
drivers/iommu/arm-smmu.c | 97 ---
drivers/iommu/arm-smmu.h | 72 +-
3 files changed, 114 insertions(+), 99 deletions(-)
diff --git a/dri
stuff), they're not ones we have any need to access.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 106 +--
1 file changed, 58 insertions(+), 48 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index e72554f
On 16/08/2019 14:00, Christoph Hellwig wrote:
Instead of taking apart the dma address in both callers do it inside
dma_cache_maint itself.
Signed-off-by: Christoph Hellwig
---
arch/arm/xen/mm.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/xen/mm.c b
Hi Jordan,
On 15/08/2019 16:33, Jordan Crouse wrote:
On Wed, Aug 07, 2019 at 04:21:38PM -0600, Jordan Crouse wrote:
(Sigh, resend. I freaked out my SMTP server)
This is part of an ongoing evolution for enabling split pagetable support for
arm-smmu. Previous versions can be found [1].
In the d
On 16/08/2019 19:12, Rob Clark wrote:
On Fri, Aug 16, 2019 at 9:58 AM Robin Murphy wrote:
Hi Jordan,
On 15/08/2019 16:33, Jordan Crouse wrote:
On Wed, Aug 07, 2019 at 04:21:38PM -0600, Jordan Crouse wrote:
(Sigh, resend. I freaked out my SMTP server)
This is part of an ongoing evolution
On 26/07/2019 09:31, Yoshihiro Shimoda wrote:
This patch adds a new dma_map_ops of get_merge_boundary() to
expose the DMA merge boundary if the domain type is IOMMU_DOMAIN_DMA.
Signed-off-by: Yoshihiro Shimoda
Reviewed-by: Simon Horman
---
drivers/iommu/dma-iommu.c | 11 +++
1 file
On 19/08/2019 16:56, Will Deacon wrote:
On Thu, Aug 15, 2019 at 07:37:20PM +0100, Robin Murphy wrote:
v1 for context: https://patchwork.kernel.org/cover/11087347/
Here's a quick v2 attempting to address all the minor comments; I've
tweaked a whole bunch of names, added some verbosity
this easy to accommodate - by simplifying the current
range checks into explicit tests that address bits above IAS are all
zero, it then follows straightforwardly to add the inverse test to
allow the all-ones case as well.
Signed-off-by: Robin Murphy
---
drivers/iommu/io-pgtable-arm.c | 7 ---
1
simply allocating a table and dealing
with the detailed TTBRn logistics themselves.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu-v3.c| 2 +-
drivers/iommu/arm-smmu.c | 9 -
drivers/iommu/io-pgtable-arm-v7s.c | 16 +++-
drivers/iommu/io-pgtable-arm.c
Between VMSAv8-64 and the various 32-bit formats, there is either one
64-bit MAIR or a pair of 32-bit MAIR0/MAIR1 or NMRR/PMRR registers.
As such, keeping two 64-bit values in io_pgtable_cfg has always been
overkill.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu-v3.c| 2 +-
drivers
xpectation that drivers will have to add to the given TCR
value anyway, let's strip it down to just the essentials that are
directly relevant to io-pgatble's inner workings - namely the address
sizes, walk attributes, and where appropriate, format selection.
Signed-off-by: Robin Murphy
--
basis from which users can
construct their own complete context.
Series based on v2 of "Arm SMMU refactoring" here:
https://patchwork.kernel.org/patch/11096263/
Robin.
Robin Murphy (4):
iommu/io-pgtable-arm: Rationalise MAIR handling
iommu/io-pgtable-arm: Rationalise TTBRn hand
mmu
driver which uses the dma-iommu api uses gfp_atomic in it's
iommu_ops::map function. But doing this wastes the memory allocators
atomic pools.
Looks reasonable to me - once we get the merges sorted out I'll take a
look at propagating the flags through to io-pgtable for the SMMU drivers
On 15/08/2019 12:09, Tom Murphy wrote:
Handle devices which defer their attach to the iommu in the dma-iommu api
Other than nitpicking the name (I'd lean towards something like
iommu_dma_deferred_attach),
Reviewed-by: Robin Murphy
Signed-off-by: Tom Murphy
---
drivers/iomm
s.
Reviewed-by: Robin Murphy
Signed-off-by: Tom Murphy
---
drivers/iommu/dma-iommu.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index 906b7fa14d3c..b9a3ab02434b 100644
--- a/drivers/iommu/dma-
On 19/08/2019 19:37, Stefan Wahren wrote:
Hi,
i tried to cross compile arm/multi_v7_defconfig with CONFIG_XEN=y with
Linux 5.3-rc5 and i'm getting this:
arch/arm/mm/dma-mapping.c: In function ‘arch_setup_dma_ops’:
arch/arm/mm/dma-mapping.c:2347:5: error: ‘struct device’ has no member
named ‘dma
In a hurry to get things ready for merging, we missed that one more
include needs moving to arm-smmu.h along with the register accessors
to prevent 32-bit builds breaking, and some missing static specifiers
made Sparse sad.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu-impl.c | 8
On 20/08/2019 11:15, Vivek Gautam wrote:
[...]
Hi Robin,
Sorry for responding late to this series. I have couple of doubts here
that I wanted to discuss.
Are we standardizing these implementation specific ops? Each vendor
implementations will have something peculiar to take care. Things are
On 19/08/2019 23:34, Jordan Crouse wrote:
On Mon, Aug 19, 2019 at 07:19:31PM +0100, Robin Murphy wrote:
Now that callers are free to use a given table for TTBR1 if they wish
(all they need do is shift the provided attributes when constructing
their final TCR value), the only remaining
On 20/08/2019 11:19, Will Deacon wrote:
On Mon, Aug 19, 2019 at 07:19:29PM +0100, Robin Murphy wrote:
TTBR1 values have so far been redundant since no users implement any
support for split address spaces. Crucially, though, one of the main
reasons for wanting to do so is to be able to manage
On 20/08/2019 11:30, Will Deacon wrote:
On Mon, Aug 19, 2019 at 07:19:31PM +0100, Robin Murphy wrote:
Now that callers are free to use a given table for TTBR1 if they wish
(all they need do is shift the provided attributes when constructing
their final TCR value), the only remaining impediment
On 20/08/2019 11:31, Will Deacon wrote:
On Mon, Aug 19, 2019 at 07:19:30PM +0100, Robin Murphy wrote:
Although it's conceptually nice for the io_pgtable_cfg to provide a
standard VMSA TCR value, the reality is that no VMSA-compliant IOMMU
looks exactly like an Arm CPU, and they all have va
On 20/08/2019 16:45, Will Deacon wrote:
To prevent any potential issues arising from speculative Address
Translation Requests from an ATS-enabled PCIe endpoint, rework our ATS
enabling/disabling logic so that we enable ATS at the SMMU before we
enable it at the endpoint, and disable things in the
On 20/08/2019 16:45, Will Deacon wrote:
When invalidating the ATC for an PCIe endpoint using ATS, we must take
care to complete invalidation of the main SMMU TLBs beforehand, otherwise
the device could immediately repopulate its ATC with stale translations.
Hooking the ATC invalidation into ->un
On 20/08/2019 17:07, Will Deacon wrote:
On Tue, Aug 20, 2019 at 04:25:56PM +0100, Robin Murphy wrote:
On 20/08/2019 11:31, Will Deacon wrote:
On Mon, Aug 19, 2019 at 07:19:30PM +0100, Robin Murphy wrote:
Although it's conceptually nice for the io_pgtable_cfg to provide a
standard VMS
On 14/08/2019 18:56, Will Deacon wrote:
The ->tlb_add_flush() callback in the io-pgtable API now looks a bit
silly:
- It takes a size and a granule, which are always the same
- It takes a 'bool leaf', which is always true
- It only ever flushes a single page
With that in mind, replace
On 21/08/2019 13:05, Will Deacon wrote:
Hi Robin,
Thanks for looking at this.
On Wed, Aug 21, 2019 at 12:42:11PM +0100, Robin Murphy wrote:
On 14/08/2019 18:56, Will Deacon wrote:
The ->tlb_add_flush() callback in the io-pgtable API now looks a bit
silly:
- It takes a size and a gran
On 21/08/2019 13:11, Will Deacon wrote:
On Tue, Aug 20, 2019 at 07:41:52PM +0100, Robin Murphy wrote:
On 20/08/2019 17:07, Will Deacon wrote:
On Tue, Aug 20, 2019 at 04:25:56PM +0100, Robin Murphy wrote:
On 20/08/2019 11:31, Will Deacon wrote:
On Mon, Aug 19, 2019 at 07:19:30PM +0100, Robin
On 21/08/2019 16:24, Will Deacon wrote:
On Wed, Aug 21, 2019 at 09:53:12PM +0800, Yong Wu wrote:
MediaTek extend the arm v7s descriptor to support up to 34 bits PA where
the bit32 and bit33 are encoded in the bit9 and bit4 of the PTE
respectively. Meanwhile the iova still is 32bits.
Regarding w
-v3: Add support for PCI ATS")
Acked-by: Robin Murphy
Signed-off-by: Will Deacon
---
drivers/iommu/arm-smmu-v3.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 3402b1bc8e94..7a368059cd7d 100644
--- a/drivers/iommu/
the opposite order.
This time it looks right :)
Reviewed-by: Robin Murphy
Signed-off-by: Will Deacon
---
drivers/iommu/arm-smmu-v3.c | 47 +++--
1 file changed, 28 insertions(+), 19 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu
On 14/08/2019 18:56, Will Deacon wrote:
In preparation for deferring TLB flushes to iommu_tlb_sync(), introduce
two new synchronous invalidation helpers to the io-pgtable API, which
allow the unmap() code to force invalidation in cases where it cannot be
deferred (e.g. when replacing a table with
->unmap() as we currently do does the
exact opposite: it ensures that the ATC is invalidated *before* the
main TLBs, which is bogus.
Move ATC invalidation into the actual (leaf) invalidation routines so
that it is always called after completing main TLB invalidation.
Reviewed-by: Robin Mur
On 2019-08-22 9:56 am, Yong Wu wrote:
On Wed, 2019-08-21 at 16:24 +0100, Will Deacon wrote:
On Wed, Aug 21, 2019 at 09:53:12PM +0800, Yong Wu wrote:
MediaTek extend the arm v7s descriptor to support up to 34 bits PA where
the bit32 and bit33 are encoded in the bit9 and bit4 of the PTE
respectiv
On 2019-08-22 11:17 am, Will Deacon wrote:
On Thu, Aug 22, 2019 at 11:08:58AM +0100, Robin Murphy wrote:
On 2019-08-22 9:56 am, Yong Wu wrote:
On Wed, 2019-08-21 at 16:24 +0100, Will Deacon wrote:
On Wed, Aug 21, 2019 at 09:53:12PM +0800, Yong Wu wrote:
MediaTek extend the arm v7s descriptor
the bandwidth just now for a deep dive into the ordering
subtleties, but on the surface I think this looks sound - provided that
we don't forget and start calling arm_smmu_atc_inv_master() directly
from anywhere other than detach.
Acked-by: Robin Murphy
Signed-off-by: Will Deacon
On 11/07/2019 16:02, Gregory CLEMENT wrote:
From: Hanna Hawa
Add specific compatible string for Marvell usage due errata of
accessing 64bits registers of ARM SMMU, in AP806.
AP806 SoC uses the generic ARM-MMU500, and there's no specific
implementation of Marvell, this compatible is used for er
On 20/08/2019 13:08, Will Deacon wrote:
Hi Gregory, Hanna,
On Thu, Jul 11, 2019 at 05:02:39PM +0200, Gregory CLEMENT wrote:
From: Hanna Hawa
This patch introduces the smmu_writeq_relaxed/smmu_readq_relaxed
helpers, as preparation to add specific Marvell work-around for
accessing 64 bits width
Hi Neil,
On 28/08/2019 12:28, Neil Armstrong wrote:
Hi Robin,
On 31/05/2019 15:47, Robin Murphy wrote:
On 31/05/2019 13:04, Tomeu Vizoso wrote:
On Wed, 29 May 2019 at 19:38, Robin Murphy wrote:
On 29/05/2019 16:09, Tomeu Vizoso wrote:
On Tue, 21 May 2019 at 18:11, Clément Péron wrote
wards compared to what we want
to do here, which I guess is more of an "atomic_unlikely_cmpxchg".
Acked-by: Robin Murphy
Cheers,
Robin.
On Wed, Aug 28, 2019 at 06:13:38AM -0700, Eric Dumazet wrote:
In commit 14bd9a607f90 ("iommu/iova: Separate atomic variables
to improve performance&q
On 30/08/2019 14:39, David Laight wrote:
From: Lu Baolu
Sent: 30 August 2019 08:17
The Intel VT-d hardware uses paging for DMA remapping.
The minimum mapped window is a page size. The device
drivers may map buffers not filling the whole IOMMU
window. This allows the device to access to possib
On 29/08/2019 23:47, Krishna Reddy wrote:
Add Nvidia SMMUv2 implementation and model info.
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/iommu/Makefile | 2 +-
drivers/iommu/arm-smmu-impl.c | 2 +
drivers/iommu/arm-smmu-nvidia.c | 97
On 29/08/2019 23:47, Krishna Reddy wrote:
Add binding doc for Nvidia's smmu-v2 implementation.
Signed-off-by: Krishna Reddy
---
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
b/Doc
On 29/08/2019 23:47, Krishna Reddy wrote:
tlb_sync hook allows nvidia smmu handle tlb sync
across multiple SMMUs as necessary.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 32
drivers/iommu/arm-smmu.c| 8 +---
drivers/iommu
On 29/08/2019 23:47, Krishna Reddy wrote:
Add global/context fault hooks to allow Nvidia SMMU implementation
handle faults across multiple SMMUs.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 127
drivers/iommu/arm-smmu.c|
On 29/08/2019 23:47, Krishna Reddy wrote:
Add DT node for T194 SMMU to enable SMMU support.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 75
1 file changed, 75 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
On 30/08/2019 17:18, Christoph Hellwig wrote:
On Fri, Aug 30, 2019 at 05:07:56PM +0200, Krzysztof Wilczynski wrote:
Move ATS function prototypes from include/linux/pci-ats.h to
include/linux/pci.h so users only need to include :
Why is that so important? Very few PCI(e) device drivers use ATS
On 30/08/2019 18:25, Krishna Reddy wrote:
+ #global-interrupts = <1>;
Shouldn't that be 3?
Interrupt line is shared between global and all context faults for each SMMU
instance.
Nvidia implementation checks for both Global and context faults on each
interrupt to an SMMU insta
On 30/08/2019 23:49, Krishna Reddy wrote:
+ if (smmu->impl->tlb_sync) {
+ smmu->impl->tlb_sync(smmu, page, sync, status);
What I'd hoped is that rather than needing a hook for this, you could just
override smmu_domain->tlb_ops from .init_context to wire up the alternate .s
On 30/08/2019 19:16, Krishna Reddy wrote:
+ARM_SMMU_MATCH_DATA(nvidia_smmuv2, ARM_SMMU_V2, NVIDIA_SMMUV2);
From the previous discussions, I got the impression that other than the
'novel' way they're integrated, the actual SMMU implementations were unmodified
Arm MMU-500s. Is that the case,
On 29/08/2019 12:14, Thierry Reding wrote:
From: Thierry Reding
This is an implementation that IOMMU drivers can use to obtain reserved
memory regions from a device tree node. It uses the reserved-memory DT
bindings to find the regions associated with a given device. These
regions will be used
On 29/08/2019 12:14, Thierry Reding wrote:
From: Thierry Reding
For device tree nodes, use the standard of_iommu_get_resv_regions()
implementation to obtain the reserved memory regions associated with a
device.
This covers the window between iommu_probe_device() setting up a default
domain a
On 23/08/2019 07:32, Vivek Gautam wrote:
Add reset hook for sdm845 based platforms to turn off
the wait-for-safe sequence.
Understanding how wait-for-safe logic affects USB and UFS performance
on MTP845 and DB845 boards:
Qcom's implementation of arm,mmu-500 adds a WAIT-FOR-SAFE logic
to address
On 07/09/2019 18:50, Rob Clark wrote:
From: Rob Clark
When games, browser, or anything using a lot of GPU buffers exits, there
can be many hundreds or thousands of buffers to unmap and free. If the
GPU is otherwise suspended, this can cause arm-smmu to resume/suspend
for each buffer, resulting
On 06/09/2019 22:44, Rob Clark wrote:
From: Rob Clark
One of the challenges we have to enable the aarch64 laptops upstream
is dealing with the fact that the bootloader enables the display and
takes the corresponding SMMU context-bank out of BYPASS. Unfortunately,
currently, the IOMMU framework
On 10/09/2019 16:34, Rob Clark wrote:
On Tue, Sep 10, 2019 at 1:14 AM Joerg Roedel wrote:
On Fri, Sep 06, 2019 at 02:44:01PM -0700, Rob Clark wrote:
@@ -674,7 +674,7 @@ int iommu_group_add_device(struct iommu_group *group,
struct device *dev)
mutex_lock(&group->mutex);
list_ad
l 4 levels.
Signed-off-by: Robin Murphy
---
drivers/iommu/io-pgtable-arm.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 9e35cd991f06..77f41c9dd9be 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/dri
ute
values borrowed from the kbase driver; at this point we'll be overriding
or ignoring pretty much all of the LPAE config, so just implement these
Mali details in a dedicated allocator instead of pretending to subclass
the standard VMSA format.
Signed-off-by: Robin Murphy
---
drivers/iommu/io-pgt
Hi all,
Here's the eagerly-awaited fix to unblock T720/T820, plus a couple of
other bits that I've collected so far. I'm not considering this as
5.3 fixes material, but it would be nice if there's any chance still
to sneak it into 5.4.
Robin.
Robin Murphy (3):
iommu/io-
g the TTBR_SHARE_OUTER bit does indeed get coherent pagetable
walks working nicely.
Making data accesses coherent seems to be more of a challenge...
Signed-off-by: Robin Murphy
---
drivers/iommu/io-pgtable-arm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/io-pgtable-arm.c b/dr
On 2019-09-11 5:20 pm, Will Deacon wrote:
On Wed, Sep 11, 2019 at 06:19:04PM +0200, Neil Armstrong wrote:
On 11/09/2019 16:42, Robin Murphy wrote:
Here's the eagerly-awaited fix to unblock T720/T820, plus a couple of
other bits that I've collected so far. I'm not considering th
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 5 +
drivers/iommu/arm-smmu.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index b7cf24402a94..76ac8c180695 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm
On 13/09/2019 12:48, Robin Murphy wrote:
Although CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is a welcome tool
for smoking out inadequate firmware, the failure mode is non-obvious
and can be confusing for end users. Add some special-case reporting of
Unidentified Stream Faults to help clarify
On 13/09/2019 15:35, Qian Cai wrote:
On Fri, 2019-09-13 at 12:48 +0100, Robin Murphy wrote:
Although CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is a welcome tool
for smoking out inadequate firmware, the failure mode is non-obvious
and can be confusing for end users. Add some special-case
me I wrote
this, but apparently I never noticed that that had already been cleaned
up by the time this got merged.
Reviewed-by: Robin Murphy
Thanks,
Robin.
Signed-off-by: Christophe JAILLET
---
drivers/iommu/arm-smmu.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/iommu/ar
On 2019-09-16 7:19 pm, Doug Anderson wrote:
[...]
1. "By firmware" might be a bit misleading. In most cases I'm aware
of the problem is in the device tree that was bundled together with
the kernel. If there are actually cases where firmware has baked in a
device tree and it got this wrong then
declared in
arm-smmu.h as per the Nvidia implementation[1], so you can then keep all
the other details private. With that change,
Reviewed-by: Robin Murphy
Thanks,
Robin.
[1]
https://lore.kernel.org/linux-arm-kernel/1567481528-31163-3-git-send-email-vdu...@nvidia.com/
+
+#endif /* _ARM_SMM
dding yet another print to the mix, also break out an
explicit ratelimit state to make sure everything stays together (and
reduce the static storage footprint a little).
CC: Douglas Anderson
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 21 -
drivers/iommu/arm-s
Now that the "leaf" flag is no longer part of an external interface,
there's no need to use it to infer a register offset at runtime when
we can just as easily encode the offset directly in its place.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 29 -
Fill in 'native' iommu_flush_ops callbacks for all the
arm_smmu_flush_ops variants, and clear up the remains of the previous
.tlb_inv_range abstraction.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 110 ++-
drivers/iommu/arm-smmu.h
.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 33 +++--
drivers/iommu/arm-smmu.h | 3 ++-
2 files changed, 17 insertions(+), 19 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index b5b4cd4cae19..cc3b7517458d 100644
--- a/drivers
Now it's just an empty wrapper.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 40 +---
drivers/iommu/arm-smmu.h | 6 +-
2 files changed, 18 insertions(+), 28 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-s
Hi all,
Off the back of Will's iommu_flush_ops work, here's an initial followup
to replace the temporary solution in arm-smmu with a full conversion.
Removing teh extra layer of indirection should generally make things a
good bit more efficient, and rather more readable to boot.
Robi
Hi John,
On 19/09/2019 09:43, John Garry wrote:
Hi all,
We have noticed a special behaviour on our arm64 D05 board when the SMMU
is enabled with regards PCI device iommu groups.
This platform does not support ACS, yet we find that all functions for a
PCI device are not grouped together:
r
On 20/09/2019 14:48, Rob Herring wrote:
Convert the Arm SMMv3 binding to the DT schema format.
Cc: Joerg Roedel
Cc: Mark Rutland
Cc: Will Deacon
Cc: Robin Murphy
Cc: iommu@lists.linux-foundation.org
Signed-off-by: Rob Herring
---
.../devicetree/bindings/iommu/arm,smmu-v3.txt | 77
Hi Tomeu,
On 23/09/2019 09:17, Tomeu Vizoso wrote:
There is some argument for taking #1 and #2 as 5.4 fixes, though - the
upcoming Mesa 19.2 release will enable T820 support on the userspace side -
so let's pick that discussion up again in a few weeks.
Ok, I'll include those two in my fixes pu
On 26/09/2019 13:37, Halil Pasic wrote:
On Mon, 23 Sep 2019 17:21:17 +0200
Christoph Hellwig wrote:
On Mon, Sep 23, 2019 at 02:34:16PM +0200, Halil Pasic wrote:
Before commit 57bf5a8963f8 ("dma-mapping: clear harmful GFP_* flags in
common code") tweaking the client code supplied GFP_* flags u
Hi Will,
Although the rc1 tag is yet to appear, today's master seems close enough
(the DRM and IOMMU pulls are landed at least) so here's the promised
rebase of these patches with tags added, and some minor commit message
improvements for good measure.
Robin.
Robin Murphy (3):
ARM Mali midgard MMU page table
format")
Tested-by: Neil Armstrong
Reviewed-by: Steven Price
Signed-off-by: Robin Murphy
---
drivers/iommu/io-pgtable-arm.c | 53 +-
1 file changed, 40 insertions(+), 13 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm.c b
r as I can test,
this should make all known Midgard variants happy.
Fixes: d08d42de6432 ("iommu: io-pgtable: Add ARM Mali midgard MMU page table
format")
Tested-by: Neil Armstrong
Reviewed-by: Steven Price
Signed-off-by: Robin Murphy
---
drivers/iommu/io-pgtable-arm.c | 7 ++
e to avoid pgprot_writecombine creating an attribute mismatch on
the CPU side, so we won't try wiring that up just yet.
Reviewed-by: Steven Price
Signed-off-by: Robin Murphy
---
drivers/iommu/io-pgtable-arm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/io-pgtable-
On 02/10/2019 06:18, Tomasz Figa wrote:
Hi Yong,
On Mon, Sep 30, 2019 at 2:42 PM Yong Wu wrote:
The commit 4d689b619445 ("iommu/io-pgtable-arm-v7s: Convert to IOMMU API
TLB sync") help move the tlb_sync of unmap from v7s into the iommu
framework. It helps add a new function "mtk_iommu_iotlb_s
On 01/10/2019 23:02, khol...@gmail.com wrote:
From: AngeloGioacchino Del Regno
To avoid context faults reset the context entirely on detach and
to ensure a fresh clean start also do a complete reset before
programming the context for domain initialization.
Signed-off-by: AngeloGioacchino Del R
On 02/10/2019 13:05, Geert Uytterhoeven wrote:
Hi Christoph,
On Fri, Aug 30, 2019 at 8:30 AM Christoph Hellwig wrote:
A helper to find the backing page array based on a virtual address.
This also ensures we do the same vm_flags check everywhere instead
of slightly different or missing ones in
Hi Kees,
On 2019-10-02 9:46 pm, Kees Cook wrote:
As we've seen from USB and other areas, we need to always do runtime
checks for DMA operating on memory regions that might be remapped. This
consolidates the (existing!) checks and makes them on by default. A
warning will be triggered for any driv
On 03/10/2019 00:58, Kees Cook wrote:
On Wed, Oct 02, 2019 at 10:15:43PM +0100, Robin Murphy wrote:
Hi Kees,
On 2019-10-02 9:46 pm, Kees Cook wrote:
As we've seen from USB and other areas, we need to always do runtime
checks for DMA operating on memory regions that might be remapped.
;arm-smmu.disable_bypass=n' to their command line or revert the
patch in their own private kernel. Of course these folks will be
less secure.
Suggested-by: Robin Murphy
Signed-off-by: Douglas Anderson
---
Hi Doug / Robin,
I ran into this breaking things on OcteonTx boards based on
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