On Tue, 7 Dec 2021 14:32:48 +0800, Zhou Wang wrote:
> The commit f115f3c0d5d8 ("iommu/arm-smmu-v3: Decrease the queue size of
> evtq and priq") decreases evtq and priq, which may lead evtq/priq to be
> full with fault events, e.g HiSilicon ZIP/SEC/HPRE have maximum 1024 queues
> in one device, ever
Hi Joerg,
Please pull these Arm SMMU updates for 5.17.
Once again, there's not a lot here. In fact, it's mostly a combination
of non-critical fixes and DT compatible string additions. Summary in
the tag.
Cheers,
Will
--->8
The following changes since commit 0fcfb00b28c0b7884635dacf38e46d60bf3
Hi Greg,
On 2021/12/13 8:50, Lu Baolu wrote:
On 12/10/21 9:23 AM, Lu Baolu wrote:
Hi Greg, Jason and Christoph,
On 12/9/21 9:20 AM, Lu Baolu wrote:
On 12/7/21 9:16 PM, Jason Gunthorpe wrote:
On Tue, Dec 07, 2021 at 10:57:25AM +0800, Lu Baolu wrote:
On 12/6/21 11:06 PM, Jason Gunthorpe wrote
On Tue, Dec 14 2021 at 22:19, Thomas Gleixner wrote:
> On Tue, Dec 14 2021 at 14:56, Nishanth Menon wrote:
>
> thanks for trying. I'll have a look again with brain awake tomorrow
> morning.
Morning was busy with other things, but I found what my sleepy brain
managed to do wrong yesterday evening.
On Wed, Dec 15, 2021 at 01:30:45PM +0800, Yong Wu wrote:
> On Tue, 2021-12-14 at 07:02 -0800, Guenter Roeck wrote:
> > On 12/13/21 11:31 PM, Yong Wu wrote:
> > > On Fri, 2021-12-10 at 12:57 -0800, Guenter Roeck wrote:
> > > > Since commit baf94e6ebff9 ("iommu/mediatek: Add device link for
> > > > s
On Wed, Dec 15 2021 at 17:18, Thomas Gleixner wrote:
> On Tue, Dec 14 2021 at 22:19, Thomas Gleixner wrote:
>> On Tue, Dec 14 2021 at 14:56, Nishanth Menon wrote:
>>
>> thanks for trying. I'll have a look again with brain awake tomorrow
>> morning.
>
> Morning was busy with other things, but I fou
The MSI core will introduce runtime allocation of MSI related data. This
data will be devres managed and has to be set up before enabling
PCI/MSI[-X]. This would introduce an ordering issue vs. pcim_release().
The setup order is:
pcim_enable_device()
devres_alloc(pcim_release...);
Allocate MSI device data on first use, i.e. when a PCI driver invokes one
of the PCI/MSI enablement functions.
Add a wrapper function to ensure that the ordering vs. pcim_msi_release()
is correct.
Signed-off-by: Thomas Gleixner
---
V4: Adopted to ensure devres ordering
---
drivers/pci/msi/msi.c
On Wed, Dec 15, 2021 at 06:16:44PM +0100, Thomas Gleixner wrote:
> The MSI core will introduce runtime allocation of MSI related data. This
> data will be devres managed and has to be set up before enabling
> PCI/MSI[-X]. This would introduce an ordering issue vs. pcim_release().
>
> The setup ord
On Wed, Dec 15, 2021 at 06:19:49PM +0100, Thomas Gleixner wrote:
> Allocate MSI device data on first use, i.e. when a PCI driver invokes one
> of the PCI/MSI enablement functions.
>
> Add a wrapper function to ensure that the ordering vs. pcim_msi_release()
> is correct.
>
> Signed-off-by: Thomas
On 17:35-20211215, Thomas Gleixner wrote:
>git://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git
> msi-v4.1-part-2
[...]
> That should cure the problem.
And it sure does. Thanks for looking closer and providing a fix.
https://gist.github.com/nmenon/9862a1c31b17fd6dfe0a30c
On Thu, 09 Dec 2021 17:35:57 +0100, Thierry Reding wrote:
> From: Thierry Reding
>
> On NVIDIA SoC's the ARM SMMU needs to interact with the memory
> controller in order to map memory clients to the corresponding stream
> IDs. Document how the nvidia,memory-controller property can be used to
> ac
> From: Tianyu Lan
> Sent: Sunday, December 12, 2021 11:14 PM
> To: KY Srinivasan ; Haiyang Zhang
> ; Stephen Hemminger ;
> wei@kernel.org; Dexuan Cui ; t...@linutronix.de;
> mi...@redhat.com; b...@alien8.de; dave.han...@linux.intel.com;
> x...@kernel.org; h...@zytor.com; da...@davemloft.net;
The find.h APIs are designed to be used only on unsigned long arguments.
This can technically result in a over-read, but it is harmless in this
case. Regardless, fix it to avoid the warning seen under -Warray-bounds,
which we'd like to enable globally:
In file included from ./include/linux/bitmap.
On Tue, Dec 14, 2021 at 05:03:12PM -0800, Roman Gushchin wrote:
> On Tue, Dec 14, 2021 at 01:57:22PM +0100, Vlastimil Babka wrote:
> > On 12/1/21 19:14, Vlastimil Babka wrote:
> > > Folks from non-slab subsystems are Cc'd only to patches affecting them,
> > > and
> > > this cover letter.
> > >
>
These macros has no reference in the tree anymore. Cleanup them.
Signed-off-by: Lu Baolu
---
include/linux/intel-svm.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/include/linux/intel-svm.h b/include/linux/intel-svm.h
index 57cceecbe37f..1b73bab7eeff 100644
--- a/include/linux/intel-
Hi Thomas,
On 17:35-20211215, Thomas Gleixner wrote:
>git://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git
> msi-v4.2-part-3
As you helped offline, summarizing the details on part3 of the series:
I was seeing failure[1] of NFS(DMA) on all TI K3 platforms:
[1.013258] ti
From: Thomas Gleixner Sent: Wednesday, December 15, 2021
8:36 AM
>
> On Wed, Dec 15 2021 at 17:18, Thomas Gleixner wrote:
>
> > On Tue, Dec 14 2021 at 22:19, Thomas Gleixner wrote:
> >> On Tue, Dec 14 2021 at 14:56, Nishanth Menon wrote:
> >>
> >> thanks for trying. I'll have a look again with
18 matches
Mail list logo
