On Thu, Oct 31, 2019 at 06:11:33PM +0300, Dmitry Osipenko wrote:
> 15.10.2019 19:29, Thierry Reding пишет:
> > From: Thierry Reding
> >
> > This new framework is currently nothing more than a registry of memory
> > controllers, with the goal being to order device probing. One use-case
> > where t
On 31/10/2019 23:34, Saravana Kannan via iommu wrote:
I looked into the iommu-map property and it shouldn't be too hard to
add support for it. Looks like we can simply hold off on probing the
root bridge device till all the iommus in its iommu-map are probed and
we should be fine.
I'm also unsu
On Thu, Oct 31, 2019 at 04:34:14PM -0700, Saravana Kannan wrote:
> > Neat, I'm trying to do the same for virtio-iommu. It needs to be modular
> > because it depends on the virtio transport, which distributions usually
> > build as a module. So far I've been managing the device links in
> > virtio-i
On Fri, Nov 01, 2019 at 12:41:48PM +0100, Jean-Philippe Brucker wrote:
[...]
> > > I'm also wondering about ACPI support.
> >
> > I'd love to add ACPI support too, but I have zero knowledge of ACPI.
> > I'd be happy to help anyone who wants to add ACPI support that allows
> > ACPI to add device
On Thu, Oct 31, 2019 at 02:31:02PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> When games, browser, or anything using a lot of GPU buffers exits, there
> can be many hundreds or thousands of buffers to unmap and free. If the
> GPU is otherwise suspended, this can cause arm-smmu to resume/suspe
On Fri, Sep 20, 2019 at 01:34:26PM +0530, Sai Prakash Ranjan wrote:
> Previous version of the patches are at [1]:
>
> QCOM's implementation of smmu-500 on sdm845 adds a hardware logic called
> wait-for-safe. This logic helps in meeting the invalidation requirements
> from 'real-time clients', such
Hi Rob,
On Mon, Oct 14, 2019 at 02:12:56PM -0500, Rob Herring wrote:
> Convert the Arm SMMv3 binding to the DT schema format.
>
> Cc: Joerg Roedel
> Cc: Mark Rutland
> Cc: Will Deacon
> Cc: Robin Murphy
> Cc: iommu@lists.linux-foundation.org
> Signed-off-by: Rob Herring
> ---
> v2:
> - Refin
On 2019-11-01 22:01, Will Deacon wrote:
On Fri, Sep 20, 2019 at 01:34:26PM +0530, Sai Prakash Ranjan wrote:
Previous version of the patches are at [1]:
QCOM's implementation of smmu-500 on sdm845 adds a hardware logic
called
wait-for-safe. This logic helps in meeting the invalidation
requirem
Hi Jean-Philippe,
Quick question while you figure out the devlink stuff with Saravana...
On Thu, Oct 31, 2019 at 08:37:58PM +0100, Jean-Philippe Brucker wrote:
> On Wed, Oct 30, 2019 at 05:57:44PM -0700, Saravana Kannan via iommu wrote:
> > > > > Obviously you need to be careful about using IOMMU
On Fri, Nov 01, 2019 at 10:49:00PM +0530, Sai Prakash Ranjan wrote:
> On 2019-11-01 22:01, Will Deacon wrote:
> > On Fri, Sep 20, 2019 at 01:34:26PM +0530, Sai Prakash Ranjan wrote:
> > > Previous version of the patches are at [1]:
> > >
> > > QCOM's implementation of smmu-500 on sdm845 adds a har
On 2019-11-01 22:55, Will Deacon wrote:
On Fri, Nov 01, 2019 at 10:49:00PM +0530, Sai Prakash Ranjan wrote:
On 2019-11-01 22:01, Will Deacon wrote:
> On Fri, Sep 20, 2019 at 01:34:26PM +0530, Sai Prakash Ranjan wrote:
> > Previous version of the patches are at [1]:
> >
> > QCOM's implementation
On Fri, 25 Oct 2019 13:47:25 +0800
Lu Baolu wrote:
> Hi,
>
> On 10/25/19 3:54 AM, Jacob Pan wrote:
> > Make use of generic IOASID code to manage PASID allocation,
> > free, and lookup. Replace Intel specific code.
> >
> > Signed-off-by: Jacob Pan
> > ---
> > drivers/iommu/intel-iommu.c | 12
01.11.2019 13:18, Thierry Reding пишет:
> On Thu, Oct 31, 2019 at 06:11:33PM +0300, Dmitry Osipenko wrote:
>> 15.10.2019 19:29, Thierry Reding пишет:
>>> From: Thierry Reding
>>>
>>> This new framework is currently nothing more than a registry of memory
>>> controllers, with the goal being to orde
On Fri, Nov 1, 2019 at 12:08 PM Will Deacon wrote:
>
> Hi Rob,
>
> On Mon, Oct 14, 2019 at 02:12:56PM -0500, Rob Herring wrote:
> > Convert the Arm SMMv3 binding to the DT schema format.
> >
> > Cc: Joerg Roedel
> > Cc: Mark Rutland
> > Cc: Will Deacon
> > Cc: Robin Murphy
> > Cc: iommu@lists.
On Fri, 25 Oct 2019 07:04:28 +
"Tian, Kevin" wrote:
> > From: Jacob Pan [mailto:jacob.jun@linux.intel.com]
> > Sent: Friday, October 25, 2019 3:55 AM
> >
> > Nested translation mode is supported in VT-d 3.0 Spec.CH 3.8.
> > With PASID granular translation type set to 0x11b, translation
>
On Fri, Nov 1, 2019 at 3:28 AM John Garry wrote:
>
> On 31/10/2019 23:34, Saravana Kannan via iommu wrote:
> > I looked into the iommu-map property and it shouldn't be too hard to
> > add support for it. Looks like we can simply hold off on probing the
> > root bridge device till all the iommus in
On Sat, 26 Oct 2019 10:22:43 +0800
Lu Baolu wrote:
> Hi,
>
> On 10/25/19 3:55 AM, Jacob Pan wrote:
> > When Shared Virtual Memory is exposed to a guest via vIOMMU,
> > scalable IOTLB invalidation may be passed down from outside IOMMU
> > subsystems. This patch adds invalidation functions that ca
On Fri, 25 Oct 2019 07:21:29 +
"Tian, Kevin" wrote:
> > From: Jacob Pan [mailto:jacob.jun@linux.intel.com]
> > Sent: Friday, October 25, 2019 3:55 AM
> >
> > When Shared Virtual Memory is exposed to a guest via vIOMMU,
> > scalable IOTLB invalidation may be passed down from outside IOMMU
On Fri, Nov 1, 2019 at 5:28 AM Lorenzo Pieralisi
wrote:
>
> On Fri, Nov 01, 2019 at 12:41:48PM +0100, Jean-Philippe Brucker wrote:
>
> [...]
>
> > > > I'm also wondering about ACPI support.
> > >
> > > I'd love to add ACPI support too, but I have zero knowledge of ACPI.
> > > I'd be happy to help
Hi all,
this series switches over xtensa to use the generic DMA remap and
uncached code. Xtensa is a little special because it uses an uncached
segment by default, but can still use page table bits for remapping
highmem. To facilitate that there is some major refactoring in the
common DMA code t
The argument isn't used anywhere, so stop passing it.
Signed-off-by: Christoph Hellwig
---
include/linux/dma-direct.h | 2 +-
kernel/dma/direct.c| 4 ++--
kernel/dma/remap.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/linux/dma-direct.h b/includ
Integrate the generic dma remapping implementation into the main flow.
This prepares for architectures like xtensa that use an uncached
segment for pages in the kernel mapping, but can also remap highmem
from CMA. To simplify that implementation we now always deduct the
page from the physical addr
For dma-direct we know that the DMA address is an encoding of the
physical address that we can trivially decode. Use that fact to
provide implementations that do not need the arch_dma_coherent_to_pfn
architecture hook. Note that we still can only support mmap of
non-coherent memory only if the ar
We can just call dma_free_contiguous directly instead of wrapping it.
Signed-off-by: Christoph Hellwig
---
include/linux/dma-direct.h | 1 -
kernel/dma/direct.c| 11 +++
kernel/dma/remap.c | 4 ++--
3 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/include
Switch xtensa over to use the generic uncached support, and thus the
generic implementations of dma_alloc_* and dma_alloc_*, which also
gains support for mmaping DMA memory. The non-working nommu DMA
support has been disabled, but could be re-enabled easily if platforms
that actually have an uncac
From: Wei Hu Sent: Tuesday, October 22, 2019 4:11 AM
>
> On Hyper-V, Generation 1 VMs can directly use VM's physical memory for
> their framebuffers. This can improve the efficiency of framebuffer and
> overall performence for VM. The physical memory assigned to framebuffer
> must be contiguous.
Update the INTEL IOMMU (VT-d) entry and add myself as the
co-maintainer. I have several years of VT-d development
experience and have actively contributed to Intel VT-d
driver during recent two years. I volunteer to take this
rule. With this role, I can better help review and test
patches.
Cc: Dav
On Fri, Nov 1, 2019 at 3:02 PM Christoph Hellwig wrote:
> this series switches over xtensa to use the generic DMA remap and
> uncached code. Xtensa is a little special because it uses an uncached
> segment by default, but can still use page table bits for remapping
> highmem. To facilitate that
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