On Mon, Feb 25, 2019 at 08:21:46AM +0800, Nicolas Boichat wrote:
> Joerg: Just to make sure, is this patch in your queue? Thanks.
It is now, thanks.
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On Mon, Feb 11, 2019 at 03:50:33PM +, Tom Murphy wrote:
> Fix typo, flush_tlb_all should be flush_iotlb_all
>
> Signed-off-by: Tom Murphy
Applied, thanks.
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On Wed, Feb 13, 2019 at 10:54:42AM -0700, Logan Gunthorpe wrote:
> iommu/vt-d: Add helper to set an IRTE to verify only the bus number
> iommu/vt-d: Allow interrupts from the entire bus for aliased devices
Applied these two to the iommu tree, thanks.
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On Mon, Feb 18, 2019 at 03:37:48PM +0100, Stanislaw Gruszka wrote:
> 0001-mt76x02u-use-usb_bulk_msg-to-upload-firmware.patch
> 0002-mt76usb-do-not-use-compound-head-page-for-SG-I-O.patch
>
> Or problem can be solved by just one of it (either first or second).
>
> Additionally I'm not 100% sure if
On Tue, Feb 19, 2019 at 11:04:50AM -0800,
sathyanarayanan.kuppusw...@linux.intel.com wrote:
> Kuppuswamy Sathyanarayanan (2):
> PCI/ATS: Add pci_prg_resp_pasid_required() interface.
> iommu/vt-d: Fix PRI/PASID dependency issue.
>
> drivers/iommu/intel-iommu.c | 4 +++-
> drivers/pci/ats.c
Hi Geert,
On Wed, Feb 20, 2019 at 02:00:50PM +0100, Geert Uytterhoeven wrote:
> This series contains a fix for an incorrect kerneldoc parameter, and
> adds the missing kerneldoc for two recently added IOMMU methods.
>
> Thanks!
>
> Geert Uytterhoeven (3):
> iommu: Fix kerneldoc for iommu_ops.f
On Tue, Feb 19, 2019 at 11:06:08AM -0800,
sathyanarayanan.kuppusw...@linux.intel.com wrote:
> Kuppuswamy Sathyanarayanan (2):
> PCI/ATS: Add pci_ats_page_aligned() interface
> iommu/vt-d: Enable ATS only if the device uses page aligned address.
>
> drivers/iommu/intel-iommu.c | 1 +
> dri
On Wed, Feb 20, 2019 at 02:05:05PM +0100, Geert Uytterhoeven wrote:
> A change made in the final version of IOMMU debugfs support replaced the
> public function iommu_debugfs_new_driver_dir() by the public dentry
> iommu_debugfs_dir in , but forgot to update both the
> implementation in iommu-debug
On Wed, Feb 20, 2019 at 07:17:45PM +, Julia Cartwright wrote:
> On Wed, Feb 20, 2019 at 10:46:31AM -0600, Julia Cartwright wrote:
> > - size = sizeof(*info) + level * sizeof(struct acpi_dmar_pci_path);
> > + size = sizeof(*info) + level * sizeof(info->path[0]);
>
> This is probably a candi
On Tue, Feb 26, 2019 at 11:05:36AM +0100, Joerg Roedel wrote:
> On Mon, Feb 18, 2019 at 03:37:48PM +0100, Stanislaw Gruszka wrote:
> > 0001-mt76x02u-use-usb_bulk_msg-to-upload-firmware.patch
> > 0002-mt76usb-do-not-use-compound-head-page-for-SG-I-O.patch
> >
> > Or problem can be solved by just on
On Fri, Feb 22, 2019 at 10:19:18AM +0800, Lu Baolu wrote:
> Lu Baolu (9):
> iommu: Add APIs for multiple domains per device
> iommu/vt-d: Move enable pasid out of CONFIG_INTEL_IOMMU_SVM
> iommu/vt-d: Add per-device IOMMU feature ops entries
> iommu/vt-d: Move common code out of iommu_att
On Tue, Feb 26, 2019 at 11:34:51AM +0100, Stanislaw Gruszka wrote:
> On Tue, Feb 26, 2019 at 11:05:36AM +0100, Joerg Roedel wrote:
> If sg->offset > PAGE_SIZE is fine then most likely we have problem with
> alignment.
The map_sg implementation in the AMD IOMMU driver uses sg_phys() which
handles t
On Mon, Feb 25, 2019 at 10:46:36AM +0800, Lu Baolu wrote:
> drivers/iommu/intel-iommu.c | 21 -
> 1 file changed, 12 insertions(+), 9 deletions(-)
Added a Fixes: tag and applied the patch, thanks.
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On Mon, Feb 25, 2019 at 08:51:22PM +, Michael Kelley wrote:
> Joerg -- What's your take on this patch set now that it has settled down? If
> you are good with it, from the Microsoft standpoint we're hoping that it
> can get into linux-next this week (given the extra week due to 5.0-rc8).
I ca
Hi Jean-Philippe,
Thanks for the patch! I think this is getting close to be applied after
the next merge window.
On Wed, Feb 20, 2019 at 02:27:59PM +, Jean-Philippe Brucker wrote:
> +int iommu_sva_bind_device(struct device *dev, struct mm_struct *mm, int
> *pasid,
> + i
On Tue, Feb 26, 2019 at 11:44:13AM +0100, Joerg Roedel wrote:
> On Tue, Feb 26, 2019 at 11:34:51AM +0100, Stanislaw Gruszka wrote:
> > On Tue, Feb 26, 2019 at 11:05:36AM +0100, Joerg Roedel wrote:
> > If sg->offset > PAGE_SIZE is fine then most likely we have problem with
> > alignment.
>
> The ma
From: Lan Tianyu
On the bare metal, enabling X2APIC mode requires interrupt remapping
function which helps to deliver irq to cpu with 32-bit APIC ID.
Hyper-V doesn't provide interrupt remapping function so far and Hyper-V
MSI protocol already supports to deliver interrupt to the CPU whose
virtual
From: Lan Tianyu
Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic,
set x2apic destination mode to physcial mode when x2apic is available
and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs have
8-bit APIC id.
Reviewed-by: Thomas Gleixner
Reviewed-by: Michael K
From: Lan Tianyu
On the bare metal, enabling X2APIC mode requires interrupt remapping
function which helps to deliver irq to cpu with 32-bit APIC ID.
Hyper-V doesn't provide interrupt remapping function so far and Hyper-V
MSI protocol already supports to deliver interrupt to the CPU whose
virtual
Hi Jean,
On 2019/1/31 22:55, Jean-Philippe Brucker wrote:
> Hi,
>
> On 31/01/2019 13:52, Zhen Lei wrote:
>> Currently, many peripherals are faster than before. For example, the top
>> speed of the older netcard is 10Gb/s, and now it's more than 25Gb/s. But
>> when iommu page-table mapping enabled
On 26/02/2019 11:17, Joerg Roedel wrote:
> Hi Jean-Philippe,
>
> Thanks for the patch! I think this is getting close to be applied after
> the next merge window.
>
> On Wed, Feb 20, 2019 at 02:27:59PM +, Jean-Philippe Brucker wrote:
>> +int iommu_sva_bind_device(struct device *dev, struct mm_
On Tue, Feb 26, 2019 at 12:49:15PM +, Jean-Philippe Brucker wrote:
> On 26/02/2019 11:17, Joerg Roedel wrote:
> > int iommu_sva_get_pasid(struct iommu_sva *handle);
> > void iommu_sva_set_exit_handler(struct iommu_sva *handle,
> > iommu_mm_exit_handle
On Tue, Feb 26, 2019 at 08:07:17PM +0800, lantianyu1...@gmail.com wrote:
> Lan Tianyu (3):
> x86/Hyper-V: Set x2apic destination mode to physical when x2apic is
> available
> HYPERV/IOMMU: Add Hyper-V stub IOMMU driver
> MAINTAINERS: Add Hyper-V IOMMU driver into Hyper-V CORE AND DRIV
On Tue, Feb 26, 2019 at 9:07 PM Joerg Roedel wrote:
>
> On Tue, Feb 26, 2019 at 08:07:17PM +0800, lantianyu1...@gmail.com wrote:
> > Lan Tianyu (3):
> > x86/Hyper-V: Set x2apic destination mode to physical when x2apic is
> > available
> > HYPERV/IOMMU: Add Hyper-V stub IOMMU driver
> >
On 2019-02-26 2:34 a.m., Joerg Roedel wrote:
> On Wed, Feb 13, 2019 at 10:54:42AM -0700, Logan Gunthorpe wrote:
>> iommu/vt-d: Add helper to set an IRTE to verify only the bus number
>> iommu/vt-d: Allow interrupts from the entire bus for aliased devices
>
> Applied these two to the iommu t
tree: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git hyper-v
head: bb564d53ed035865e85f16acf217dee93705e518
commit: 67938046f7991474f94ad85da3f8e43c0cf510c0 [1/3] x86/Hyper-V: Set x2apic
destination mode to physical when x2apic is available
config: x86_64-randconfig-s2-02270010
ARM Mali midgard GPUs have a few differences from standard 64-bit
stage 1 page tables.
The 3rd level page entry bits are 0x1 instead of 0x3 for page entries.
The access flags are not read-only and unprivileged, but read and write.
This is similar to stage 2 entries, but the memory attributes fiel
Hi Rob,
On 26/02/2019 18:17, Rob Herring wrote:
ARM Mali midgard GPUs have a few differences from standard 64-bit
stage 1 page tables.
The 3rd level page entry bits are 0x1 instead of 0x3 for page entries.
The access flags are not read-only and unprivileged, but read and write.
This is similar
On Tue, Feb 26, 2019 at 1:25 PM Robin Murphy wrote:
>
> Hi Rob,
>
> On 26/02/2019 18:17, Rob Herring wrote:
> > ARM Mali midgard GPUs have a few differences from standard 64-bit
> > stage 1 page tables.
> >
> > The 3rd level page entry bits are 0x1 instead of 0x3 for page entries.
> >
> > The acce
This reverts commit d222e42e88168fd67e6d131984b86477af1fc256.
The original change breaks omap dss:
omapdss_dispc 58001000.dispc:
dispc_errata_i734_wa_init: dma_alloc_writecombine failed
Let's revert it first and then find a safer solution instead.
Reported-by: Tony Lindgren
Signed-o
tree: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git hyper-v
head: bb564d53ed035865e85f16acf217dee93705e518
commit: 004240dcc222119271ce9559af4250ab00053621 [2/3] iommu/hyper-v: Add
Hyper-V stub IOMMU driver
config: x86_64-randconfig-s3-02270001 (attached as .config)
compiler:
tree: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git hyper-v
head: bb564d53ed035865e85f16acf217dee93705e518
commit: 004240dcc222119271ce9559af4250ab00053621 [2/3] iommu/hyper-v: Add
Hyper-V stub IOMMU driver
config: x86_64-randconfig-r0-02270133 (attached as .config)
compiler:
tree: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git hyper-v
head: bb564d53ed035865e85f16acf217dee93705e518
commit: 67938046f7991474f94ad85da3f8e43c0cf510c0 [1/3] x86/Hyper-V: Set x2apic
destination mode to physical when x2apic is available
config: x86_64-randconfig-x014-201908
On 2019-02-26 8:23 pm, Nicolin Chen wrote:
This reverts commit d222e42e88168fd67e6d131984b86477af1fc256.
The original change breaks omap dss:
omapdss_dispc 58001000.dispc:
dispc_errata_i734_wa_init: dma_alloc_writecombine failed
Let's revert it first and then find a safer solution
* Robin Murphy [190226 23:36]:
> On 2019-02-26 8:23 pm, Nicolin Chen wrote:
> > This reverts commit d222e42e88168fd67e6d131984b86477af1fc256.
> >
> > The original change breaks omap dss:
> > omapdss_dispc 58001000.dispc:
> > dispc_errata_i734_wa_init: dma_alloc_writecombine failed
>
On Tue, Feb 26, 2019 at 11:35:44PM +, Robin Murphy wrote:
> On 2019-02-26 8:23 pm, Nicolin Chen wrote:
> > This reverts commit d222e42e88168fd67e6d131984b86477af1fc256.
> >
> > The original change breaks omap dss:
> > omapdss_dispc 58001000.dispc:
> > dispc_errata_i734_wa_init: d
On 2019-02-26 8:05 pm, Rob Herring wrote:
On Tue, Feb 26, 2019 at 1:25 PM Robin Murphy wrote:
Hi Rob,
On 26/02/2019 18:17, Rob Herring wrote:
ARM Mali midgard GPUs have a few differences from standard 64-bit
stage 1 page tables.
The 3rd level page entry bits are 0x1 instead of 0x3 for page
Hi Will, Robin:
Do you have time to review these patches? Hope you can give me some opinions.
On 2019/2/19 15:54, Zhen Lei wrote:
> This patch series include two parts:
> 1. Patch1-2 use dummy STE tables with "ste abort" hardware feature to abort
> unexpected
>devices accessing. For more
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