On Thu, May 11, 2017 at 04:40:51PM +0200, Rafael J. Wysocki wrote:
> On Thursday, May 11, 2017 09:45:25 AM Will Deacon wrote:
> > On Thu, May 11, 2017 at 02:26:02AM +0200, Rafael J. Wysocki wrote:
> > > On Wednesday, May 10, 2017 05:01:55 PM Geetha sowjanya wrote:
> > > > From: Linu Cherian
> > >
IORT revision C has been published with a number of new SMMU
implementation identifiers; define them.
CC: Rafael J. Wysocki
CC: Robert Moore
CC: Lv Zheng
Signed-off-by: Robin Murphy
---
include/acpi/actbl2.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/acpi/actbl2.h b/i
Revision C of IORT now allows us to identify ARM MMU-401 and the Cavium
ThunderX implementation; wire them up so that the appropriate quirks get
enabled when booting with ACPI.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 8
1 file changed, 8 insertions(+)
diff --git a/dr
On Wed, Apr 26, 2017 at 06:12:02PM +0800, Liu, Yi L wrote:
> From: "Liu, Yi L"
Hi Alex,
In this patchset, I'm trying to add two new IOCTL cmd for Shared
Virtual Memory virtualization. One for binding guest PASID Table
and one for iommu tlb invalidation from guest. ARM has similar
requirement on
On Tue, May 09, 2017 at 03:55:20PM +0800, Xiao Guangrong wrote:
>
>
> On 04/26/2017 06:12 PM, Liu, Yi L wrote:
> >From: "Liu, Yi L"
> >
> >This patch adds IOCTL processing in vfio_iommu_type1 for
> >VFIO_IOMMU_SVM_BIND_TASK. Binds the PASID table bind by
> >calling iommu_ops->bind_pasid_table to
On Fri, May 12, 2017 at 3:54 PM, Will Deacon wrote:
> On Thu, May 11, 2017 at 04:40:51PM +0200, Rafael J. Wysocki wrote:
>> On Thursday, May 11, 2017 09:45:25 AM Will Deacon wrote:
>> > On Thu, May 11, 2017 at 02:26:02AM +0200, Rafael J. Wysocki wrote:
>> > > On Wednesday, May 10, 2017 05:01:55 PM
Hi Yi,
On 26/04/17 11:12, Liu, Yi L wrote:
> From: "Liu, Yi L"
>
> This patch adds VFIO_IOMMU_TLB_INVALIDATE to propagate IOMMU TLB
> invalidate request from guest to host.
>
> In the case of SVM virtualization on VT-d, host IOMMU driver has
> no knowledge of caching structure updates unless th
From: Linu Cherian
Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas.
1. Errata ID #74
SMMU register alias Page 1 is not implemented
2. Errata ID #126
SMMU doesnt support unique IRQ lines and also MSI for gerror,
eventq and cmdq-sync
The following patchset does software wor
From: Linu Cherian
Cavium ThunderX2 SMMU implementation doesn't support page 1 register space
and PAGE0_REGS_ONLY option is enabled as an errata workaround.
This option when turned on, replaces all page 1 offsets used for
EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets.
SMMU r
From: Linu Cherian
Cavium ThunderX2 implementation doesn't support second page in SMMU
register space. Hence, resource size is set as 64k for this model.
Signed-off-by: Linu Cherian
Signed-off-by: Geetha Sowjanya
---
drivers/acpi/arm64/iort.c | 10 +-
1 file changed, 9 insertions(+),
From: Geetha Sowjanya
Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq
lines for gerror, eventq and cmdq-sync.
This patch addresses the issue by checking if any interrupt sources are
using same irq number, then they are registered as shared irqs.
Signed-off-by: Geetha
On Wed, 26 Apr 2017 18:12:04 +0800
"Liu, Yi L" wrote:
> From: "Liu, Yi L"
>
> This patch adds VFIO_IOMMU_TLB_INVALIDATE to propagate IOMMU TLB
> invalidate request from guest to host.
>
> In the case of SVM virtualization on VT-d, host IOMMU driver has
> no knowledge of caching structure updat
On Wed, 26 Apr 2017 18:12:02 +0800
"Liu, Yi L" wrote:
> From: "Liu, Yi L"
>
> This patch adds VFIO_IOMMU_SVM_BIND_TASK for potential PASID table
> binding requests.
>
> On VT-d, this IOCTL cmd would be used to link the guest PASID page table
> to host. While for other vendors, it may also be u
On Wed, 26 Apr 2017 18:12:03 +0800
"Liu, Yi L" wrote:
> From: "Liu, Yi L"
>
> This patch adds IOCTL processing in vfio_iommu_type1 for
> VFIO_IOMMU_SVM_BIND_TASK. Binds the PASID table bind by
> calling iommu_ops->bind_pasid_table to link the whole
> PASID table to pIOMMU.
>
> For VT-d, it is
On Wed, 26 Apr 2017 18:11:58 +0800
"Liu, Yi L" wrote:
> From: Jacob Pan
>
> Virtual IOMMU was proposed to support Shared Virtual Memory (SVM) use
> case in the guest:
> https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg05311.html
>
> As part of the proposed architecture, when a SVM capa
On Wed, 26 Apr 2017 18:12:00 +0800
"Liu, Yi L" wrote:
> From: "Liu, Yi L"
>
> When a SVM capable device is assigned to a guest, the first level page
> tables are owned by the guest and the guest PASID table pointer is
> linked to the device context entry of the physical IOMMU.
>
> Host IOMMU d
On Wed, 26 Apr 2017 18:12:01 +0800
"Liu, Yi L" wrote:
> From: Jacob Pan
>
> This patch adds Intel VT-d specific function to implement
> iommu_do_invalidate API.
>
> The use case is for supporting caching structure invalidation
> of assigned SVM capable devices. Emulated IOMMU exposes queue
> i
On Wed, 26 Apr 2017 18:11:59 +0800
"Liu, Yi L" wrote:
> From: Jacob Pan
>
> Add Intel VT-d ops to the generic iommu_bind_pasid_table API
> functions.
>
> The primary use case is for direct assignment of SVM capable
> device. Originated from emulated IOMMU in the guest, the request goes
> throu
Hi Linu,
[auto build test ERROR on arm64/for-next/core]
[also build test ERROR on v4.11 next-20170512]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Geetha-sowjanya/Cavium-ThunderX2-SMMUv3
Hi Linu,
[auto build test ERROR on arm64/for-next/core]
[also build test ERROR on v4.11 next-20170512]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Geetha-sowjanya/Cavium-ThunderX2-SMMUv3
On Sat, May 13, 2017 at 6:03 AM, kbuild test robot wrote:
> Hi Linu,
>
> [auto build test ERROR on arm64/for-next/core]
> [also build test ERROR on v4.11 next-20170512]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improve the system]
&g
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