Hi Jeffy,
Am Mittwoch, 10. Mai 2017, 18:28:12 CEST schrieb Jeffy Chen:
> This patch removes the build dependency on ARM, so we can build on arm64
> as well.
>
> Signed-off-by: Jeffy Chen
> ---
>
> drivers/iommu/Kconfig | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/iommu/Kcon
This patch removes the build dependency on ARM, so we can build on arm64
as well.
Signed-off-by: Jeffy Chen
---
drivers/iommu/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index 6ee3a25..cb26f45 100644
--- a/drivers/iommu/Kconfig
+++ b
From: Linu Cherian
Add SMMUv3 model definition for ThunderX2.
Signed-off-by: Linu Cherian
Signed-off-by: Geetha Sowjanya
---
include/acpi/actbl2.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
index faa9f2c..76a6f5d 100644
--- a/include/ac
From: Linu Cherian
Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas.
1. Errata ID #74
SMMU register alias Page 1 is not implemented
2. Errata ID #126
SMMU doesnt support unique IRQ lines and also MSI for gerror,
eventq and cmdq-sync
The following patchset does software wor
From: Linu Cherian
Cavium ThunderX2 implementation doesn't support second page in SMMU
register space. Hence, resource size is set as 64k for this model.
Signed-off-by: Linu Cherian
Signed-off-by: Geetha Sowjanya
---
drivers/acpi/arm64/iort.c | 10 +-
1 file changed, 9 insertions(+),
From: Geetha Sowjanya
Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq
lines for gerror, eventq and cmdq-sync.
This patch addresses the issue by checking if any interrupt sources are
using same irq number, then they are registered as shared irqs.
Signed-off-by: Geetha
From: Linu Cherian
Cavium ThunderX2 SMMU implementation doesn't support page 1 register space
and PAGE0_REGS_ONLY option is enabled as an errata workaround.
This option when turned on, replaces all page 1 offsets used for
EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets.
SMMU r
Hi Jean,
On 27.02.2017 20:54, Jean-Philippe Brucker wrote:
+/*
+ * Returns -ENOSYS if ATS is not supported either by the device or by the SMMU
+ */
+static int arm_smmu_enable_ats(struct arm_smmu_master_data *master)
+{
+ int ret;
+ size_t stu;
+ struct pci_dev *pdev;
+ s
On 10/05/17 13:54, Tomasz Nowicki wrote:
> Hi Jean,
>
> On 27.02.2017 20:54, Jean-Philippe Brucker wrote:
>> +/*
>> + * Returns -ENOSYS if ATS is not supported either by the device or by
>> the SMMU
>> + */
>> +static int arm_smmu_enable_ats(struct arm_smmu_master_data *master)
>> +{
>> +int r
From: CQ Tang
A driver would need to know if there are any active references to a
a PASID before cleaning up its resources. This function helps check
if there are any active users of a PASID before it can perform any
recovery on that device.
To: Joerg Roedel
To: linux-ker...@vger.kernel.org
To:
From: CQ Tang
Requires: https://patchwork.kernel.org/patch/9593891
After a FLR, pci-states need to be restored. This patch saves PASID features
and PRI reqs cached.
Cc: Jean-Phillipe Brucker
Cc: David Woodhouse
Cc: iommu@lists.linux-foundation.org
Signed-off-by: CQ Tang
Signed-off-by: Asho
From: CQ Tang
Requires: https://patchwork.kernel.org/patch/9593891
After a FLR, pci-states need to be restored. This patch saves PASID features
and PRI reqs cached.
Cc: Jean-Phillipe Brucker
Cc: David Woodhouse
Cc: iommu@lists.linux-foundation.org
Signed-off-by: CQ Tang
Signed-off-by: Ashok
From: CQ Tang
A driver would need to know if there are any active references to a
a PASID before cleaning up its resources. This function helps check
if there are any active users of a PASID before it can perform any
recovery on that device.
To: Joerg Roedel
To: linux-ker...@vger.kernel.org
To:
On Wednesday, May 10, 2017 05:01:55 PM Geetha sowjanya wrote:
> From: Linu Cherian
>
> Add SMMUv3 model definition for ThunderX2.
>
> Signed-off-by: Linu Cherian
> Signed-off-by: Geetha Sowjanya
This is an ACPICA change, but you have not included the ACPICA maintainers
into your original CC l
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