On Tue, Dec 20, 2016 at 09:29:21PM -0600, Rob Herring wrote:
> On Fri, Dec 16, 2016 at 01:19:29PM +, Robin Murphy wrote:
> > The current SMR masking support using a 2-cell iommu-specifier is
> > primarily intended to handle individual masters with large and/or
> > complex Stream ID assignments;
On Tue, Dec 6, 2016 at 9:03 AM, Joerg Roedel wrote:
> On Mon, Dec 05, 2016 at 08:09:07PM +0800, Xunlei Pang wrote:
>> drivers/iommu/intel-iommu.c | 19 +++
>> 1 file changed, 19 insertions(+)
>
> Applied, thanks.
Joerg:
This didn't seem to make the 4.10 merge window. Was that o
On Tue, Jan 03, 2017 at 08:23:23AM -0700, Myron Stowe wrote:
> This didn't seem to make the 4.10 merge window. Was that on purpose?
> Any idea when you might include this in a pull request for Linus?
I will collect fixes this week and send them to Linus, they will also
include this patch.
With the introduction of the new iommu_{register/get}_instance()
interface in commit e4f10ffe4c9b ("iommu: Make of_iommu_set/get_ops() DT
agnostic") (based on struct fwnode_handle as look-up token, so firmware
agnostic) to register IOMMU instances with the core IOMMU layer there is
no reason to kee
TODO maybe we want two options, one to enable stalling, and 2nd to punt
handling to wq? I haven't needed to use mm APIs from fault handler yet
(although it is something that I think we'll want some day). Perhaps
stalling support is limited to just letting driver dump some extra
debugging informat
Will,
I meant to scrape something together a bit sooner. I wanted to check if
this was in line with what you were thinking for upstream alternative to
reverting "iommu/arm-smmu: Disable stalling faults for all endpoints".
(Third patch is semi-unrelated, but I'd prefer to only have my rate-
limit
Let the iommu user ask the iommu to terminate the transaction without
printing any error msg via -EFAULT return.
(Alternatively, look for -ENOSYS return instead to trigger the msg?)
Signed-off-by: Rob Clark
---
drivers/iommu/arm-smmu.c | 12 ++--
1 file changed, 10 insertions(+), 2 dele
At least on the db820c I have, with the firmware I have, I'm not seeing
the SS bit set, even though the iommu is in a stalled state. So for
this implementation ignore not having SS bit set.
Signed-off-by: Rob Clark
---
drivers/iommu/arm-smmu.c | 6 ++
1 file changed, 6 insertions(+)
diff -
On Tue, Jan 03, 2017 at 04:30:55PM -0500, Rob Clark wrote:
> At least on the db820c I have, with the firmware I have, I'm not seeing
> the SS bit set, even though the iommu is in a stalled state. So for
> this implementation ignore not having SS bit set.
The SS bit gets set if SCTLR.CFCFG is set
