Stephen Warren wrote @ Fri, 1 Nov 2013 18:05:09 +0100:
> > What are the requirements for Tegra? If the IOMMU isn't initialised, does it
> > act as a passthrough?
>
> I believe so, yes. In particular we have the following register bits:
>
> 1) Register bit AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DON
On 11/01/2013 10:34 AM, Will Deacon wrote:
> On Fri, Nov 01, 2013 at 04:08:52PM +, Stephen Warren wrote:
>> On 10/31/2013 01:39 PM, Will Deacon wrote:
>>> On Thu, Oct 31, 2013 at 07:25:25PM +, Stephen Warren wrote:
On 10/31/2013 01:16 PM, Stephen Warren wrote:
> Hmm. That's interes
On 11/01/2013 10:34 AM, Will Deacon wrote:
> On Fri, Nov 01, 2013 at 04:08:52PM +, Stephen Warren wrote:
>> On 10/31/2013 01:39 PM, Will Deacon wrote:
>>> On Thu, Oct 31, 2013 at 07:25:25PM +, Stephen Warren wrote:
On 10/31/2013 01:16 PM, Stephen Warren wrote:
> Hmm. That's interes
On Fri, Nov 01, 2013 at 04:08:52PM +, Stephen Warren wrote:
> On 10/31/2013 01:39 PM, Will Deacon wrote:
> > On Thu, Oct 31, 2013 at 07:25:25PM +, Stephen Warren wrote:
> >> On 10/31/2013 01:16 PM, Stephen Warren wrote:
> >>> Hmm. That's interesting. I see that the ARM SMMU has a list of th
On 10/31/2013 01:39 PM, Will Deacon wrote:
> On Thu, Oct 31, 2013 at 07:25:25PM +, Stephen Warren wrote:
>> On 10/31/2013 01:16 PM, Stephen Warren wrote:
>>> Hmm. That's interesting. I see that the ARM SMMU has a list of the
>>> clients it affects, whereas this Tegra series puts information int
On Thu, 31 Oct 2013 20:39:41 +0100
Will Deacon wrote:
> On Thu, Oct 31, 2013 at 07:25:25PM +, Stephen Warren wrote:
> > On 10/31/2013 01:16 PM, Stephen Warren wrote:
> > > Hmm. That's interesting. I see that the ARM SMMU has a list of the
> > > clients it affects, whereas this Tegra series pu
On Thu, 31 Oct 2013 20:16:18 +0100
Stephen Warren wrote:
> Hmm. That's interesting. I see that the ARM SMMU has a list of the
> clients it affects, whereas this Tegra series puts information into each
> client device about the SMMU(s) that affect it. Is it better to flip the
> Tegra binding aroun
On Thu, 31 Oct 2013 18:40:29 +0100
Mark Rutland wrote:
> For the ARM SMMU binding, each device has a #stream-id-cells property
> describing how many IDs it has, and then the SMMU node has a phandle+args
> linkage to each of the devices attached to it, describing their stream IDs.
> While this doe
On Thu, Oct 31, 2013 at 07:25:25PM +, Stephen Warren wrote:
> On 10/31/2013 01:16 PM, Stephen Warren wrote:
> > Hmm. That's interesting. I see that the ARM SMMU has a list of the
> > clients it affects, whereas this Tegra series puts information into each
> > client device about the SMMU(s) tha
On 10/31/2013 01:16 PM, Stephen Warren wrote:
> On 10/31/2013 11:40 AM, Mark Rutland wrote:
>> On Thu, Oct 31, 2013 at 08:18:08AM +, Hiroshi Doyu wrote:
>>> Stephen Warren wrote @ Wed, 30 Oct 2013 23:44:04
>>> +0100:
>>>
> + host1x {
> + compatible = "nvidia,tegra30-host1x", "
On Thu, Oct 31, 2013 at 07:13:01PM +, Stephen Warren wrote:
> On 10/31/2013 12:02 PM, Will Deacon wrote:
> > On Thu, Oct 31, 2013 at 05:40:29PM +, Mark Rutland wrote:
> >> For the ARM SMMU binding, each device has a #stream-id-cells property
> >> describing how many IDs it has, and then the
On 10/31/2013 02:18 AM, Hiroshi Doyu wrote:
> Stephen Warren wrote @ Wed, 30 Oct 2013 23:44:04
> +0100:
>
>>> + host1x {
>>> + compatible = "nvidia,tegra30-host1x", "simple-bus";
>>> + nvidia,memory-clients = <&smmu TEGRA_SWGROUP_HC>;
>>> +
>>> + gr
On 10/31/2013 11:40 AM, Mark Rutland wrote:
> On Thu, Oct 31, 2013 at 08:18:08AM +, Hiroshi Doyu wrote:
>> Stephen Warren wrote @ Wed, 30 Oct 2013 23:44:04
>> +0100:
>>
+ host1x {
+ compatible = "nvidia,tegra30-host1x", "simple-bus";
+ nvidia,memory-clients =
On 10/31/2013 12:02 PM, Will Deacon wrote:
> On Thu, Oct 31, 2013 at 05:40:29PM +, Mark Rutland wrote:
>> For the ARM SMMU binding, each device has a #stream-id-cells property
>> describing how many IDs it has, and then the SMMU node has a phandle+args
>> linkage to each of the devices attached
On Thu, Oct 31, 2013 at 05:40:29PM +, Mark Rutland wrote:
> For the ARM SMMU binding, each device has a #stream-id-cells property
> describing how many IDs it has, and then the SMMU node has a phandle+args
> linkage to each of the devices attached to it, describing their stream IDs.
> While thi
On Thu, Oct 31, 2013 at 08:18:08AM +, Hiroshi Doyu wrote:
> Stephen Warren wrote @ Wed, 30 Oct 2013 23:44:04
> +0100:
>
> > > + host1x {
> > > + compatible = "nvidia,tegra30-host1x", "simple-bus";
> > > + nvidia,memory-clients = <&smmu TEGRA_SWGROUP_HC>;
> > > +
Stephen Warren wrote @ Wed, 30 Oct 2013 23:44:04 +0100:
> > + host1x {
> > + compatible = "nvidia,tegra30-host1x", "simple-bus";
> > + nvidia,memory-clients = <&smmu TEGRA_SWGROUP_HC>;
> > +
> > + gr3d {
> > + compatible = "nvidia,t
On 10/18/2013 04:26 AM, Hiroshi Doyu wrote:
> This provides the info about which swgroups a device belongs to. This
> info is passed from DT. This is necessary for the unified SMMU driver
> diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt
> b/Documentation/devicetree/b
On Fri, 18 Oct 2013 13:26:55 +0300, Hiroshi Doyu wrote:
> This provides the info about which swgroups a device belongs to. This
> info is passed from DT. This is necessary for the unified SMMU driver
> among Tegra SoCs since each has different H/W accelerators.
>
> Signed-off-by: Hiroshi Doyu
>
This provides the info about which swgroups a device belongs to. This
info is passed from DT. This is necessary for the unified SMMU driver
among Tegra SoCs since each has different H/W accelerators.
Signed-off-by: Hiroshi Doyu
---
.../bindings/iommu/nvidia,tegra30-smmu.txt | 16
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