Stephen Warren wrote @ Fri, 1 Nov 2013 17:54:37 +0100:
> On 10/31/2013 02:17 AM, Hiroshi Doyu wrote:
> > Stephen Warren wrote @ Wed, 30 Oct 2013 23:33:32
> > +0100:
> ...
> > Right.
> > "memory client ID" is used to find out MC_SMMU__ASID_0
> > register. This register is used to associate to a
On 10/31/2013 02:17 AM, Hiroshi Doyu wrote:
> Stephen Warren wrote @ Wed, 30 Oct 2013 23:33:32
> +0100:
...
> Right.
> "memory client ID" is used to find out MC_SMMU__ASID_0
> register. This register is used to associate to address
> space(AS). == H/W. can be attached to any AS.
>
>> Is "swgr
> > The ARM SMMU refers to these as "stream IDs", as that's the architected name
> > that appears in all the hardware documentation. If "swgroup" is the term
> > used
> > in the hardware documentation I think it makes sense to stick with it, as
> > long
> > as there's a description in the binding
Mark Rutland wrote @ Thu, 31 Oct 2013 18:31:33 +0100:
> > Assuming "swgroup" is "memory client ID", why can't the driver just
> > create a list/... of known swgroups at runtime, based on the swgroup
> > values that each device uses, which would presumably be either
> > hard-coded in the client de
On Thu, Oct 31, 2013 at 05:31:33PM +, Mark Rutland wrote:
> On Wed, Oct 30, 2013 at 10:33:32PM +, Stephen Warren wrote:
> > I'm afraid I still don't quite understand what a swgroup is.
> >
> > IIUC, the HW works like this based on comments in a previous patch:
> >
> > Each bus-master atta
On Wed, Oct 30, 2013 at 10:33:32PM +, Stephen Warren wrote:
> On 10/18/2013 04:26 AM, Hiroshi Doyu wrote:
> > This provides the info about which H/W Accelerators are supported on
> > Tegra SoC. This info is passed from DT. This is necessary to have the
> > unified SMMU driver among Tegra SoCs.
On Fri, Oct 18, 2013 at 11:26:51AM +0100, Hiroshi Doyu wrote:
> This provides the info about which H/W Accelerators are supported on
> Tegra SoC. This info is passed from DT. This is necessary to have the
> unified SMMU driver among Tegra SoCs. Instead of using platform data,
> DT passes "nvidia,sw
Stephen Warren wrote @ Wed, 30 Oct 2013 23:33:32 +0100:
> > + are required. This unique ID info can be used to calculate
> > + MC_SMMU__ASID_0 offset and HOTRESET bit.
>
> I'm afraid I still don't quite understand what a swgroup is.
>
> IIUC, the HW works like this based on comments in a prev
On 10/18/2013 04:26 AM, Hiroshi Doyu wrote:
> This provides the info about which H/W Accelerators are supported on
> Tegra SoC. This info is passed from DT. This is necessary to have the
> unified SMMU driver among Tegra SoCs. Instead of using platform data,
> DT passes "nvidia,swgroups" now. DT is
On 10/24/2013 02:58 AM, Grant Likely wrote:
> On Fri, 18 Oct 2013 13:26:51 +0300, Hiroshi Doyu wrote:
>> This provides the info about which H/W Accelerators are supported on
>> Tegra SoC. This info is passed from DT. This is necessary to have the
>> unified SMMU driver among Tegra SoCs. Instead of
On Fri, 18 Oct 2013 13:26:51 +0300, Hiroshi Doyu wrote:
> This provides the info about which H/W Accelerators are supported on
> Tegra SoC. This info is passed from DT. This is necessary to have the
> unified SMMU driver among Tegra SoCs. Instead of using platform data,
> DT passes "nvidia,swgroup
This provides the info about which H/W Accelerators are supported on
Tegra SoC. This info is passed from DT. This is necessary to have the
unified SMMU driver among Tegra SoCs. Instead of using platform data,
DT passes "nvidia,swgroups" now. DT is mandatory in Tegra.
Signed-off-by: Hiroshi Doyu
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