Hi Jean,
On 2020/11/11 21:57, Jean-Philippe Brucker wrote:
Hi Baolu,
Thanks for the review. I'm only now reworking this and realized I've never
sent a reply, sorry about that.
On Wed, May 20, 2020 at 02:42:21PM +0800, Lu Baolu wrote:
Hi Jean,
On 2020/5/20 1:54, Jean-Philippe Brucker wrote:
Hi Xiang,
Thank you for reviewing this. I forgot to send a reply, sorry for the
delay.
On Fri, May 29, 2020 at 05:18:27PM +0800, Xiang Zheng wrote:
> Hi,
>
> On 2020/5/20 1:54, Jean-Philippe Brucker wrote:
> > Some systems allow devices to handle I/O Page Faults in the core mm. For
> > example s
Hi Baolu,
Thanks for the review. I'm only now reworking this and realized I've never
sent a reply, sorry about that.
On Wed, May 20, 2020 at 02:42:21PM +0800, Lu Baolu wrote:
> Hi Jean,
>
> On 2020/5/20 1:54, Jean-Philippe Brucker wrote:
> > Some systems allow devices to handle I/O Page Faults i
Hi,
On 2020/5/20 1:54, Jean-Philippe Brucker wrote:
> Some systems allow devices to handle I/O Page Faults in the core mm. For
> example systems implementing the PCIe PRI extension or Arm SMMU stall
> model. Infrastructure for reporting these recoverable page faults was
> added to the IOMMU core b
Hi Jean,
On 2020/5/20 1:54, Jean-Philippe Brucker wrote:
Some systems allow devices to handle I/O Page Faults in the core mm. For
example systems implementing the PCIe PRI extension or Arm SMMU stall
model. Infrastructure for reporting these recoverable page faults was
added to the IOMMU core by
Some systems allow devices to handle I/O Page Faults in the core mm. For
example systems implementing the PCIe PRI extension or Arm SMMU stall
model. Infrastructure for reporting these recoverable page faults was
added to the IOMMU core by commit 0c830e6b3282 ("iommu: Introduce device
fault report
