Ho Robin,
On 04/22/2016 04:49 PM, Robin Murphy wrote:
> On 22/04/16 13:00, Eric Auger wrote:
>> Hi Robin,
>> On 04/22/2016 01:31 PM, Robin Murphy wrote:
>>> On 20/04/16 16:58, Eric Auger wrote:
Hi Robin,
On 04/20/2016 02:47 PM, Robin Murphy wrote:
> Hi Eric,
>
> On 19/04/16 17
On 22/04/16 13:00, Eric Auger wrote:
Hi Robin,
On 04/22/2016 01:31 PM, Robin Murphy wrote:
On 20/04/16 16:58, Eric Auger wrote:
Hi Robin,
On 04/20/2016 02:47 PM, Robin Murphy wrote:
Hi Eric,
On 19/04/16 17:56, Eric Auger wrote:
Introduce a new DOMAIN_ATTR_MSI_MAPPING domain attribute. If sup
Hi Robin,
On 04/22/2016 01:31 PM, Robin Murphy wrote:
> On 20/04/16 16:58, Eric Auger wrote:
>> Hi Robin,
>> On 04/20/2016 02:47 PM, Robin Murphy wrote:
>>> Hi Eric,
>>>
>>> On 19/04/16 17:56, Eric Auger wrote:
Introduce a new DOMAIN_ATTR_MSI_MAPPING domain attribute. If supported,
this m
On 20/04/16 16:58, Eric Auger wrote:
Hi Robin,
On 04/20/2016 02:47 PM, Robin Murphy wrote:
Hi Eric,
On 19/04/16 17:56, Eric Auger wrote:
Introduce a new DOMAIN_ATTR_MSI_MAPPING domain attribute. If supported,
this means the MSI addresses need to be mapped in the IOMMU.
x86 IOMMUs typically do
Hi Robin,
On 04/20/2016 02:47 PM, Robin Murphy wrote:
> Hi Eric,
>
> On 19/04/16 17:56, Eric Auger wrote:
>> Introduce a new DOMAIN_ATTR_MSI_MAPPING domain attribute. If supported,
>> this means the MSI addresses need to be mapped in the IOMMU.
>>
>> x86 IOMMUs typically don't expose the attribute
Hi Eric,
On 19/04/16 17:56, Eric Auger wrote:
Introduce a new DOMAIN_ATTR_MSI_MAPPING domain attribute. If supported,
this means the MSI addresses need to be mapped in the IOMMU.
x86 IOMMUs typically don't expose the attribute since on x86, MSI write
transaction addresses always are within the
Introduce a new DOMAIN_ATTR_MSI_MAPPING domain attribute. If supported,
this means the MSI addresses need to be mapped in the IOMMU.
x86 IOMMUs typically don't expose the attribute since on x86, MSI write
transaction addresses always are within the 1MB PA region [FEE0_h -
FEF0_000h] window whi
