On Fri, 14 Mar 2014 13:17:26 +0100, Tomasz Figa wrote:
> Hi KyongHo,
>
> On 14.03.2014 06:06, Cho KyongHo wrote:
> > This adds gate clocks of all System MMUs and their master IPs
> > that are not apeared in clk-exynos5250.c and clk-exynos5420.c
> > Also fixes GATE_IP_ACP to 0x18800 and changed GAT
Hi KyongHo,
On 14.03.2014 06:06, Cho KyongHo wrote:
This adds gate clocks of all System MMUs and their master IPs
that are not apeared in clk-exynos5250.c and clk-exynos5420.c
Also fixes GATE_IP_ACP to 0x18800 and changed GATE_DA to GATE
for System MMU clocks in clk-exynos4.c
Signed-off-by: Cho
This adds gate clocks of all System MMUs and their master IPs
that are not apeared in clk-exynos5250.c and clk-exynos5420.c
Also fixes GATE_IP_ACP to 0x18800 and changed GATE_DA to GATE
for System MMU clocks in clk-exynos4.c
Signed-off-by: Cho KyongHo
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.../devicetree/bindings/clock/exynos5250
