On 06/08/15 17:16, Will Deacon wrote:
Hi Tirumalesh,
I think this looks pretty good now, just one small comment below.
On Wed, Aug 05, 2015 at 05:54:28PM +0100, Tirumalesh Chalamarla wrote:
[...]
-#define TTBRn_HI_ASID_SHIFT16
+#define TTBRn_ASID_SHIFT 48
#define
Hi Tirumalesh,
I think this looks pretty good now, just one small comment below.
On Wed, Aug 05, 2015 at 05:54:28PM +0100, Tirumalesh Chalamarla wrote:
> The SMMU architecture defines two different behaviors when 64-bit
> registers are written with 32-bit writes. The first behavior causes
> zero
The SMMU architecture defines two different behaviors when 64-bit
registers are written with 32-bit writes. The first behavior causes
zero extension into the upper 32-bits. The second behavior splits a
64-bit register into "normal" 32-bit register pairs.
On some buggy implementations, registers
