On 8/1/2018 12:29 AM, Christoph Hellwig wrote:
I asked this question to Tony Luck before. If I remember right,
his answer was:
CPU guarantees outstanding writes to be flushed when a register write
instruction is executed and an additional barrier instruction is not
needed.
That would be great.
On Tue, Jul 31, 2018 at 11:41:23PM -0700, ok...@codeaurora.org wrote:
> I asked this question to Tony Luck before. If I remember right,
> his answer was:
>
> CPU guarantees outstanding writes to be flushed when a register write
> instruction is executed and an additional barrier instruction is not
+ my new email
On 2018-07-31 10:20, Christoph Hellwig wrote:
memory-barriers.txt has been updated with the following requirement.
"When using writel(), a prior wmb() is not needed to guarantee that the
cache coherent memory writes have completed before writing to the MMIO
region."
The current
memory-barriers.txt has been updated with the following requirement.
"When using writel(), a prior wmb() is not needed to guarantee that the
cache coherent memory writes have completed before writing to the MMIO
region."
The current writeX() and iowriteX() implementations on ia64 are not
satisfyi
