From: Jay Cornwall
Do not disassociate the process page tables from a PASID during VM
invalidation. Invalidate the IOMMU TLB and IOTLBs before invalidation.
L2 translations may fail during VM range invalidation. The current
implementation associates an empty page table with a PASID within
the cr
From: Jay Cornwall
get_user_pages requires caller to hold a read lock on mmap_sem.
Signed-off-by: Jay Cornwall
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu_v2.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/amd_iommu_v2.c b/drivers/iommu/amd_iommu_
From: Suravee Suthikulpanit
In reality, the spec can only support 16-bit PASID since
INVALIDATE_IOTLB_PAGES and COMPLETE_PPR_REQUEST commands only allow 16-bit
PASID. So, we updated the PASID_MASK accordingly and invoke BUG_ON
if the hardware is reporting PASmax more than 16-bit.
Besides, max PA
From: Suravee Suthikulpanit
According to IOMMUv2, max PASID is defined as ((2^(PASmax+1)) - 1)
using the value from MMIOx30[PASmax] register. The current does not
determine this correctly. Also the PASID_MASK should be determined by
max PASID instead of hardcoding value of 0xf.
Adding logic
From: Jay Cornwall
This patch corrects the PASID format in the INVALIDATE_IOTLB_PAGES
command, which was caused by incorrect information in
the AMD IOMMU Architectural Specification v2.01 document.
Incorrect format:
cmd->data[0][16:23] = PASID[7:0]
cmd->data[1][16:27] = PAS
From: Steven L Kinney
Add functionality to check the availability of the AMD IOMMU Performance
Counters and export this functionality to other core drivers, such as in this
case, a perf AMD IOMMU PMU. This feature is not bound to any specific AMD
family/model other than the presence of the IOMMU
From: Suravee Suthikulpanit
These patches implement the AMD IOMMU Performance Counter functionality
via custom perf PMU and implement static counting for various IOMMU
translations.
1) Extend the AMD IOMMU initialization to include performance
counter enablement.
2) The perf AMD
From: Suravee Suthikulpanit
Implement a perf PMU to handle IOMMU performance counters and events.
The PMU only supports counting mode (e.g. perf stat). Since the counters
are shared across all cores, the PMU is implemented as "system-wide" mode.
To invoke the AMD IOMMU PMU, issue a perf tool com
From: Suravee Suthikulpanit
This patch set implements framework for handling errors reported via IOMMU
event log. It also implements mechanism to filter/suppress error messages when
IOMMU hardware generates large amount event logs, which is often caused by
devices performing invalid operations
From: Suravee Suthikulpanit
Remove old event printing logic and hook up with the new event
handling logic in amd_iommu_fault.c
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu.c | 85 -
1 file changed, 6 insertions(+), 79 deletions(
From: Suravee Suthikulpanit
Add error handling/reporting/filtering logic which uses the user-specified
amd_iommu_log option to determine the log reporting behavior.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/Makefile |2 +-
drivers/iommu/amd_iommu_fault.c | 368 ++
From: Suravee Suthikulpanit
Adding amd_iommu_log command line option to allow "default", "verbose" and
"debug"
IOMMU error logging level in kernel log.
Signed-off-by: Suravee Suthikulpanit
---
Documentation/kernel-parameters.txt | 10 ++
drivers/iommu/amd_iommu_init.c | 17 ++
From: Suravee Suthikulpanit
These patches implement the AMD IOMMU Performance Counter functionality
via custom perf PMU and implement static counting for various IOMMU
translations.
1) Extend the AMD IOMMU initialization to include performance
counter enablement.
2) The perf AMD
From: Suravee Suthikulpanit
Implement a perf PMU to handle IOMMU performance counters and events.
The PMU only supports counting mode (e.g. perf stat). Since the counters
are shared across all cores, the PMU is implemented as "system-wide" mode.
To invoke the AMD IOMMU PMU, issue a perf tool com
From: Steven L Kinney
Add functionality to check the availability of the AMD IOMMU Performance
Counters and export this functionality to other core drivers, such as in this
case, a perf AMD IOMMU PMU. This feature is not bound to any specific AMD
family/model other than the presence of the IOMMU
From: Suravee Suthikulpanit
In the current interrupt handling scheme, there are as many threads as
the number of IOMMUs. Each thread is created and assigned to an IOMMU at
the time of registering interrupt handlers (request_threaded_irq).
When an IOMMU HW generates an interrupt, the irq handler (
From: Suravee Suthikulpanit
In the current interrupt handling scheme, there are as many threads as
the number of IOMMUs. Each thread is created and assigned to an IOMMU at
the time of registering interrupt handlers (request_threaded_irq).
When an IOMMU HW generates an interrupt, the irq handler (
From: Suravee Suthikulpanit
The IOMMU interrupt handling in bottom half must clear the PPR log interrupt
and event log interrupt bits to re-enable the interrupt. This is done by
writing 1 to the memory mapped register to clear the bit. Due to hardware bug,
if the driver tries to clear this bit wh
From: Suravee Suthikulpanit
This patch set contains two patches which affect IOMMU interrupt handling.
Patch 1 Implements the workaround for hardware issue when handling interrupts
and independent of patch 2. Patch 2 Modify interrupt handling thread to only
handle IOMMU interrupt on per-thread
From: Suravee Suthikulpanit
Add logic to decode AMD IOMMU event flag based on information from AMD IOMMU
specification.
This should simplify debugging IOMMU errors. Also, dump DTE information in
some additional
cases.
Example (default): The flags is now decoded.
AMD-Vi: Event logged [INVALID_
From: Suravee Suthikulpanit
Adding new command line option "amd-iommu=verbose" to allow verbose print out
in dmesg.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu_init.c |4
drivers/iommu/amd_iommu_types.h |2 ++
2 files changed, 6 insertions(+)
diff --git a/dr
From: Suravee Suthikulpanit
This patch set add detail event log information for AMD IOMMU in dmesg when
booting with
"amd-iommu=verbose".
Suravee Suthikulpanit (2):
iommu/amd: Adding new command line option "amd-iommu=verbose"
iommu/amd: Add logic to decode AMD IOMMU event flag
drivers/io
From: Suravee Suthikulpanit
Add logic to decode AMD IOMMU event flag based on information from AMD IOMMU
specification.
This should simplify debugging IOMMU errors. Also, dump DTE information in
additional cases.
This is an example:
AMD-Vi: Event logged [INVALID_DEVICE_REQUEST device=51:00.0
From: Suravee Suthikulpanit
The IOMMU interrupt handling in bottom half must clear the PPR log interrupt
and event log interrupt bits to re-enable the interrupt. This is done by
writing 1 to the memory mapped register to clear the bit. Due to hardware bug,
if the driver tries to clear this bit wh
From: Suravee Suthikulpanit
Add logic to decode AMD IOMMU event flag based on information from AMD IOMMU
specification.
This should simplify debugging IOMMU errors. Also, dump DTE information in
additional cases.
This is an example:
AMD-Vi: Event logged [IO_PAGE_FAULT device=51:00.0 domain=0x
From: Suravee Suthikulpanit
Add logic to decode AMD IOMMU event flag based on information from AMD IOMMU
specification.
This should simplify debugging IOMMU errors. Also, dump DTE information in
additional cases.
Signed-off-by: Suravee Suthikulpanit
---
Changelog:
V2:
* Fix printing
From: Suravee Suthikulpanit
Current driver does not clear the IOMMU event log interrupt bit
in the IOMMU status register after processing an interrupt.
This causes the IOMMU hardware to generate event log interrupt only once.
This has been observed in both IOMMU v1 and V2 hardware.
This patch cle
From: Suravee Suthikulpanit
Add logic to decode AMD IOMMU event flag based on information from AMD IOMMU
specification.
This should simplify debugging IOMMU errors. Also, dump DTE information in
additional cases.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu.c | 161
From: Suravee Suthikulpanit
Add IOMMU event log injection interface for testing event flag decoding logic.
This interface allows users to specify device id, event flag, and event types
via debugfs.
echo 0x300 > /sys/kernel/debug/amd-iommu-evninj/devid // (e.g. Bus:Dev.fun
3:0.0)
echo 0xfff > /
From: Suravee Suthikulpanit
Typically, IOMMU events are logged into the event log. Current driver
processes each event
in the log when the hardware generate an MSI interrupt. It reports event type,
device ID,
raw status flag, and etc. in the kernel log (dmesg)
1. The first patch improve even
From: Suravee Suthikulpanit
The IOMMU may stop processing page translations due to a perceived lack
of credits for writing upstream peripheral page service request (PPR)
or event logs. If the L2B miscellaneous clock gating feature is enabled
the IOMMU does not properly register credits after the
From: Suravee Suthikulpanit
Changes in V3:
* Add proper commit message
* Change logic to avoid unnecessary indentaion
Changes in V2:
* Fix logic that check the processor model.
* Clear write enable bit after apply workaround
* Change function name
Commit
From: Suravee Suthikulpanit
Changes from V1:
* Fix logic that check the processor model.
* Clear writing enable bit after apply the workaround
* Change function name
Signed-off-by: Suravee Suthikulpanit
diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
index 81837b0.
From: Suravee Suthikulpanit
This patch implements workaround for the AMD Family15h Model10-1Fh erratum 746.
(http://support.amd.com/us/Processor_TechDocs/48931_15h_Mod_10h-1Fh_Rev_Guide.pdf)
Signed-off-by: Suravee Suthikulpanit
diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_i
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