trigger a
fault event. So let's revert f115f3c0d5d8.
In fact, if an implementation of SMMU really does not need so long evtq
and priq, value of IDR1_EVTQS and IDR1_PRIQS can be set to proper ones.
Signed-off-by: Zhou Wang
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 5 ++---
1 file change
On 2021/4/2 1:11, Will Deacon wrote:
> On Thu, Apr 01, 2021 at 05:47:19PM +0200, Jean-Philippe Brucker wrote:
>> The SMMU provides a Stall model for handling page faults in platform
>> devices. It is similar to PCIe PRI, but doesn't require devices to have
>> their own translation cache. Instead, f
On 2021/2/27 0:29, Jean-Philippe Brucker wrote:
> Hi Zhou,
>
> On Fri, Feb 26, 2021 at 05:43:27PM +0800, Zhou Wang wrote:
>> On 2021/2/1 19:14, Jean-Philippe Brucker wrote:
>>> Hi Zhou,
>>>
>>> On Mon, Feb 01, 2021 at 09:18:42AM +0800, Zhou W
On 2021/2/1 19:14, Jean-Philippe Brucker wrote:
> Hi Zhou,
>
> On Mon, Feb 01, 2021 at 09:18:42AM +0800, Zhou Wang wrote:
>>> @@ -1033,8 +1076,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain
>>> *smmu_domain, int ssid,
>>> FI
On 2021/2/9 20:01, Greg KH wrote:
> On Tue, Feb 09, 2021 at 07:58:15PM +0800, Zhou Wang wrote:
>> On 2021/2/9 17:37, Greg KH wrote:
>>> On Tue, Feb 09, 2021 at 05:17:46PM +0800, Zhou Wang wrote:
>>>> On 2021/2/8 6:02, Andy Lutomirski wrote:
>>>>>
>&g
On 2021/2/9 17:37, Greg KH wrote:
> On Tue, Feb 09, 2021 at 05:17:46PM +0800, Zhou Wang wrote:
>> On 2021/2/8 6:02, Andy Lutomirski wrote:
>>>
>>>
>>>> On Feb 7, 2021, at 12:31 AM, Zhou Wang wrote:
>>>>
>>>> SVA(share virtual
On 2021/2/8 5:51, Arnd Bergmann wrote:
> On Sun, Feb 7, 2021 at 9:18 AM Zhou Wang wrote:
>
>> diff --git a/arch/arm64/include/asm/unistd32.h
>> b/arch/arm64/include/asm/unistd32.h
>> index cccfbbe..3f49529 100644
>> --- a/arch/arm64/include/asm/unistd32.h
&
On 2021/2/8 6:02, Andy Lutomirski wrote:
>
>
>> On Feb 7, 2021, at 12:31 AM, Zhou Wang wrote:
>>
>> SVA(share virtual address) offers a way for device to share process virtual
>> address space safely, which makes more convenient for user space device
>> dr
pin page cases in
other places, can_do_mlock is used to check permission and input
parameters.
Signed-off-by: Zhou Wang
Signed-off-by: Sihang Chen
Suggested-by: Barry Song
---
arch/arm64/include/asm/unistd.h | 2 +-
arch/arm64/include/asm/unistd32.h | 2 +
fs/Makefile
/msg3805205.html
Zhou Wang (2):
mempinfd: Add new syscall to provide memory pin
selftests/vm: add mempinfd test
arch/arm64/include/asm/unistd.h | 2 +-
arch/arm64/include/asm/unistd32.h | 2 +
fs/Makefile | 1 +
fs/mempinfd.c
This test gets a fd from new mempinfd syscall and creates multiple threads
to do pin/unpin memory.
Signed-off-by: Zhou Wang
Suggested-by: Barry Song
---
tools/testing/selftests/vm/Makefile | 1 +
tools/testing/selftests/vm/mempinfd.c | 131 ++
2 files
On 2021/2/4 23:58, Robin Murphy wrote:
> On 2021-01-29 09:06, Zhou Wang wrote:
>> This patch adds debug interfaces for SMMUv3 driver in sysfs. It adds debug
>> related files under /sys/kernel/debug/iommu/smmuv3.
>>
>> User should firstly set device and pasid to pci_dev
On 2021/2/4 5:38, Will Deacon wrote:
> On Wed, Feb 03, 2021 at 11:15:18AM +0800, Zhou Wang wrote:
>> On 2021/1/29 17:06, Zhou Wang wrote:
>>> This RFC series is the followed patch of this discussion:
>>> https://www.spinics.net/lists/arm-kernel/msg866187.html.
>>
On 2021/1/29 17:06, Zhou Wang wrote:
> This RFC series is the followed patch of this discussion:
> https://www.spinics.net/lists/arm-kernel/msg866187.html.
>
> Currently there is no debug interface about SMMUv3 driver, which makes it
> not convenient when we want to dump some in
On 2021/2/1 19:14, Jean-Philippe Brucker wrote:
> Hi Zhou,
>
> On Mon, Feb 01, 2021 at 09:18:42AM +0800, Zhou Wang wrote:
>>> @@ -1033,8 +1076,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain
>>> *smmu_domain, int ssid,
>>> FI
On 2021/1/27 23:43, Jean-Philippe Brucker wrote:
> The SMMU provides a Stall model for handling page faults in platform
> devices. It is similar to PCIe PRI, but doesn't require devices to have
> their own translation cache. Instead, faulting transactions are parked
> and the OS is given a chance t
Export page table walk needed functions and macros, then page table dump
in later debug interface could be used directly.
Signed-off-by: Zhou Wang
---
drivers/iommu/io-pgtable-arm.c | 47 +-
drivers/iommu/io-pgtable-arm.h | 43
Export arm_smmu_get_cd_ptr and arm_smmu_get_step_for_sid to let debug
interface to get related cd and ste.
Signed-off-by: Zhou Wang
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 ---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++
2 files changed, 6 insertions(+), 3 deletions
d page table, related device and pasid are set in pci_dev and
pasid files as above.
Signed-off-by: Zhou Wang
---
drivers/iommu/Kconfig | 11 +
drivers/iommu/arm/arm-smmu-v3/Makefile | 1 +
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +
drivers/iommu/arm/arm-smmu-
her to dump SMMU registers and cmd/event/pri queues.
I am not sure this series is in the right way, so let's post it out and have a
discussion. Looking forward to any feedback.
Zhou Wang (3):
iommu/arm-smmu-v3: Export cd/ste get functions
iommu/io-pgtable: Export page table walk needed fu
On 2021/1/25 23:47, Jason Gunthorpe wrote:
> On Mon, Jan 25, 2021 at 04:34:56PM +0800, Zhou Wang wrote:
>
>> +static int uacce_pin_page(struct uacce_pin_container *priv,
>> + struct uacce_pin_address *addr)
>> +{
>> +unsigned int f
On 2021/1/25 17:28, Greg Kroah-Hartman wrote:
> On Mon, Jan 25, 2021 at 04:34:56PM +0800, Zhou Wang wrote:
>> +static int uacce_pin_page(struct uacce_pin_container *priv,
>> + struct uacce_pin_address *addr)
>> +{
>> +unsigned int flag
r one file
will be unpinned in file release process.
Signed-off-by: Zhou Wang
Signed-off-by: Sihang Chen
Suggested-by: Barry Song
---
Changes v1 -> v2:
- Some tiny fixes
- Follow Greg's suggestion to get mm-list and iommu-list involved.
v1: https://lwn.net/Articles/843432/
---
drivers/
;>
>> Signed-off-by: Jean-Philippe Brucker
>> ---
>> Cc: Arnd Bergmann
>> Cc: Greg Kroah-Hartman
>> Cc: Zhangfei Gao
>> Cc: Zhou Wang
>> ---
>> drivers/misc/uacce/uacce.c | 32 +---
>> 1 file change
On 2020/6/23 23:04, Bjorn Helgaas wrote:
> On Fri, Jun 19, 2020 at 10:26:54AM +0800, Zhangfei Gao wrote:
>> Have studied _DSM method, two issues we met comparing using quirk.
>>
>> 1. Need change definition of either pci_host_bridge or pci_dev, like adding
>> member can_stall,
>> while pci system d
On 2020/9/29 6:13, Will Deacon wrote:
> On Mon, 28 Sep 2020 16:32:02 +0800, Zhou Wang wrote:
>> In arm_smmu_evtq_thread, reading event queue is from consumer pointer,
>> which has no address dependency on producer pointer, prog_reg(MMIO) and
>> event queue memory(Normal mem
will be got.
Add rmb to make sure to get correct event queue entry value.
Signed-off-by: Zhou Wang
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
hind SMMUv3\n");
> + return -ENODEV;
> + }
> +
> ops = (struct pci_ecam_ops *)of_device_get_match_data(dev);
> return pci_host_common_probe(pdev, ops);
> }
>
Acked-by: Zhou Wang
Thanks,
Zhou
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On 2017/3/10 3:00, Sricharan R wrote:
> This series calls the dma ops configuration for the devices
> at a generic place so that it works for all busses.
> The dma_configure_ops for a device is now called during
> the device_attach callback just before the probe of the
> bus/driver is called. Simil
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