On 2/4/2016 11:53 AM, Andreas Hartmann wrote:
On 02/04/2016 at 04:47 PM, Suravee Suthikulanit wrote:
Hi Andreas,
On 2/4/2016 8:53 AM, Andreas Hartmann wrote:
Hello!
The following happens with Linux 4.4.1 during boot on an MSI A78M-E35
board. Additionally, I attached the complete dmesg.
I
On 12/14/2015 9:08 AM, Joerg Roedel wrote:
On Fri, Dec 11, 2015 at 04:54:38PM -0600, Suravee Suthikulpanit wrote:
Current driver makes assumption that device with devid zero is always
included in the range of devices to be managed by IOMMU. However,
certain FW does not include devid zero in IVRS
On 4/1/2015 7:58 AM, Joerg Roedel wrote:
Hi,
here are a few fixes and enhancements for the AMD IOMMU
driver for the next merge window. They are tested on
different versions of AMD IOMMUs. Please review.
Thanks,
Joerg
Joerg Roedel (9):
iommu/amd: Use BUS_NOTIFY_REMOVED_DEVICE
iom
On 5/6/2014 2:11 PM, Suravee Suthikulanit wrote:
On 5/6/2014 1:14 PM, Joerg Roedel wrote:
On Mon, Apr 28, 2014 at 05:27:46PM -0500, Suthikulpanit, Suravee wrote:
From: Jay Cornwall
get_user_pages requires caller to hold a read lock on mmap_sem.
Right, but can't we just swit
On 5/6/2014 1:14 PM, Joerg Roedel wrote:
On Mon, Apr 28, 2014 at 05:27:46PM -0500, Suthikulpanit, Suravee wrote:
From: Jay Cornwall
get_user_pages requires caller to hold a read lock on mmap_sem.
Right, but can't we just switch to get_user_pages_fast instead?
Joerg
You're right.
On 3/5/2014 4:35 PM, Joerg Roedel wrote:
- cmd->data[1] = pasid & PASID_MASK;
>+ cmd->data[1] = pasid & amd_iommu_max_pasid;
... masking out the other bits is redundant.
Joerg
Agree. I can take out the masking stuff here, but I think we should be
using the
Joerg,
Other commands can still support upto 20-bit PASID. As I mentioned,
there is still no system with more than 16-bit PASID.
Either way, I have also replaced the PASID_MASK with the value derived
from MMIOx30h[PASmax] of the IOMMU Extended Feature register instead.
This should allow us no
On 1/29/2014 12:03 PM, Will Deacon wrote:
On Wed, Jan 29, 2014 at 05:57:16PM +, Suravee Suthikulanit wrote:
On 1/29/2014 11:29 AM, Will Deacon wrote:
On Wed, Jan 29, 2014 at 05:26:35PM +, Suravee Suthikulanit wrote:
On 1/29/2014 11:16 AM, Andreas Herrmann wrote:
On Wed, Jan 29, 2014
On 1/29/2014 11:29 AM, Will Deacon wrote:
On Wed, Jan 29, 2014 at 05:26:35PM +, Suravee Suthikulanit wrote:
On 1/29/2014 11:16 AM, Andreas Herrmann wrote:
On Wed, Jan 29, 2014 at 11:59:12AM -0500, Suravee Suthikulanit wrote:
Actually, we are using 32 on the AMD system. So, do you think we
On 1/29/2014 11:16 AM, Andreas Herrmann wrote:
On Wed, Jan 29, 2014 at 11:59:12AM -0500, Suravee Suthikulanit wrote:
On 1/29/2014 10:57 AM, Rob Herring wrote:
diff --git a/include/linux/of.h b/include/linux/of.h
index 276c546..24e1b28 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
On 1/29/2014 10:57 AM, Rob Herring wrote:
diff --git a/include/linux/of.h b/include/linux/of.h
>>index 276c546..24e1b28 100644
>>--- a/include/linux/of.h
>>+++ b/include/linux/of.h
>>@@ -67,7 +67,7 @@ struct device_node {
>> #endif
>> };
>>
>>-#define MAX_PHANDLE_ARGS 8
>>+#define MAX_PHANDLE
On 1/17/2014 5:08 AM, Andreas Herrmann wrote:
arm-smmu driver uses of_parse_phandle_with_args when parsing DT
information to determine stream IDs for a master device.
Thus the number of stream IDs per master device is bound by
MAX_PHANDLE_ARGS.
To support Calxeda ECX-2000 hardware arm-smmu driv
Jorge,
Please let me know if you have any other questions/concerns.
Thanks,
Suravee
On 5/28/2013 5:45 PM, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit
These patches implement the AMD IOMMU Performance Counter functionality
via custom perf PMU and implement static countin
On 5/28/2013 7:18 AM, Joerg Roedel wrote:
On Fri, May 17, 2013 at 02:43:32PM -0500, Suthikulpanit, Suravee wrote:
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index b0684e4..fcbd3b8 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -30,7
Joerg,
Thanks for the review. I'll post new patch set to address your comment
shortly.
Suravee
On 5/28/2013 6:07 AM, Joerg Roedel wrote:
On Fri, May 17, 2013 at 02:43:31PM -0500, Suthikulpanit, Suravee wrote:
From: Steven L Kinney
Add functionality to check the availability of the AMD IO
On 5/21/2013 4:11 AM, Peter Zijlstra wrote:
On Mon, May 20, 2013 at 10:41:29AM -0500, Suravee Suthikulanit wrote:
Peter,
Please let me know if you have any questions/concerns regarding the PMU
implementation.
Looks good, how would you like to go about merging this? Should I push
it through
Peter,
Please let me know if you have any questions/concerns regarding the PMU
implementation.
Joerg,
Please let me know if you have any questions/concerns regarding the
changes in the IOMMU driver.
Thank you,
Suravee
On 5/17/2013 2:43 PM, suravee.suthikulpa...@amd.com wrote:
From: Surav
On 5/14/2013 2:09 AM, Peter Zijlstra wrote:
On Mon, May 13, 2013 at 04:43:44PM -0500, steven.kin...@amd.com wrote:
+static void init_iommu_perf_ctr(struct amd_iommu *iommu)
+{
+ u32 val = 0xabcd, val2 = 0;
+
+ if (!iommu_feature(iommu, FEATURE_PC))
+ return;
+
+ a
On 4/29/2013 4:42 PM, Don Dutile wrote:
On 04/29/2013 04:34 PM, Duran, Leo wrote:
I'm wondering if resetting the IOMMU at init-time (once) would clear
any BIOS induced noise.
Leo
Well, depends what you mean by 'reset'
(a) setting it up for OS use is effectively a reset, but doesn't
quies
On 4/29/2013 3:10 PM, Don Dutile wrote:
On 04/29/2013 03:45 PM, Suravee Suthikulanit wrote:
Joerg,
We are in the process of implementing AMD IOMMU error handling, and I
would like some comments from you and the community.
Currently, the AMD IOMMU driver only reports events from the event
Joerg,
We are in the process of implementing AMD IOMMU error handling, and I
would like some comments from you and the community.
Currently, the AMD IOMMU driver only reports events from the event log
in the dmesg, and does not try to handle them in case of errors. AMD
IOMMU errors can be c
Joerg,
Do you have any other concerns about this patch set?
Thank you,
Suravee
On 4/10/2013 10:57 AM, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit
This patch set add detail event log information for AMD IOMMU in dmesg when
booting with
"amd-iommu=verbose".
Suravee Suth
On 4/18/2013 3:06 PM, Joerg Roedel wrote:
Yes, but the irq-thread function itself executes the handler function
repeatedly until the IRQTF_RUNTHREAD bit is cleared. And every new
interrupt will set this bit again. So when there is a new interrupt
while our handler function runs the handler will b
g the
interrupt disabled.
Suravee
On 4/18/2013 11:28 AM, Joerg Roedel wrote:
On Thu, Apr 18, 2013 at 11:13:19AM -0500, Suravee Suthikulanit wrote:
This workaround is required for both event log and ppr log. Your
patch is only taking care of the event log.
Right, thanks for the notice. Here i
Joerg,
Do you have any more concerns about this patch?
Thank you,
Suravee
On 4/10/2013 10:57 AM, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit
Add logic to decode AMD IOMMU event flag based on information from AMD IOMMU
specification.
This should simplify debugging IOMMU
Joerg,
This workaround is required for both event log and ppr log. Your patch
is only taking care of the event log.
Suravee
On 4/18/2013 11:02 AM, Joerg Roedel wrote:
On Mon, Apr 15, 2013 at 02:07:46AM -0500, suravee.suthikulpa...@amd.com wrote:
drivers/iommu/amd_iommu.c | 145 +
On 4/9/2013 3:29 PM, Joerg Roedel wrote:
On Tue, Apr 09, 2013 at 10:13:02PM +0200, Joerg Roedel wrote:
Add two new kernel commandline parameters ivrs_ioapic and
ivrs_hpet to override the Id->DeviceId mapping from the IVRS
ACPI table. This can be used to work around broken BIOSes to
get interrupt
On 4/10/2013 11:21 AM, Shuah Khan wrote:
Good feature. Do you also plan to add decode logic for these flags.
For example, RZ is only meaningful when PR=1, RW is only meaningful
when
PR=1, TR=0, and I=0, and so on? This additional logic will be useful.
Reviewed-by: Shuah Khan
-- Shuah
Additional
On 4/9/2013 4:41 AM, Joerg Roedel wrote:
On Tue, Apr 02, 2013 at 07:06:50PM -0500, Suthikulpanit, Suravee wrote:
From: Suravee Suthikulpanit
Add logic to decode AMD IOMMU event flag based on information from AMD IOMMU
specification.
This should simplify debugging IOMMU errors. Also, dump DTE
On 4/9/2013 4:49 AM, Joerg Roedel wrote:
On Wed, Apr 03, 2013 at 06:19:04PM -0500, Suthikulpanit, Suravee wrote:
In the system with multiple IOMMU,this handling scheme complicates the
synchronization of the IOMMU data structures and status registers as
there could be multiple threads competing f
On 4/8/2013 9:50 AM, Borislav Petkov wrote:
Independent from Joerg's feedback on this, I have only one question:
you're not seriously considering on dumping this "Note:..." line above
on*every* IO-PF, right?
Boris,
If you think that is obvious, I can get rid of this also.
Suravee
Joerg,
Do you have any feedback about this patch?
Thanks,
Suravee
On 4/3/2013 6:19 PM, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit
The IOMMU interrupt handling in bottom half must clear the PPR log interrupt
and event log interrupt bits to re-enable the interrupt. This
On 4/2/2013 9:35 AM, Joerg Roedel wrote:
On Wed, Mar 27, 2013 at 06:51:34PM -0500, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit
Add IOMMU event log injection interface for testing event flag decoding logic.
This interface allows users to specify device id, event flag, and e
On 4/2/2013 9:33 AM, Joerg Roedel wrote:
Hi Suravee,
On Wed, Mar 27, 2013 at 06:51:23PM -0500, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit
Add logic to decode AMD IOMMU event flag based on information from AMD IOMMU
specification.
This should simplify debugging IOMMU err
Hi Joerg,
Do you have any comments or feedback about this patch set?
Thank you,
Suravee
On 3/27/2013 6:51 PM, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit
Add logic to decode AMD IOMMU event flag based on information from AMD IOMMU
specification.
This should simplify
Hi,
Would you please provide the kernel log and the dump of ACPI (from tools
like "acpidump")? These should help debugging the issue.
Thank you,
Suravee
*From:* Donald Dutile mailto:ddut...@redhat.com>>
*Date:* March 7, 2013, 3:08:57 AM GMT+08:00
*To:* JapHack mailto:japh...@yahoo.com>>
*Cc
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