On 9/14/20 5:44 PM, Christoph Hellwig wrote:
> DMA_ATTR_NON_CONSISTENT is a no-op except on PARISC and some mips
> configs, so don't set it in this ARM specific driver.
Hm, PARICS and ARM capitalized but mips in lower case? :-)
> Signed-off-by: Christoph Hellwig
[...]
MBR, Sergei
__
Hello!
On 9/8/20 7:47 PM, Christoph Hellwig wrote:
> Driver that select DMA_OPS need to depend on HAS_DMA support to
> work. The vop driver was missing that dependency, so add it, and also
> add a nother depends in DMA_OPS itself. That won't fix the issue due
Another? :-)
> to how the Kcon
Hello!
On 14.07.2020 0:35, Lad Prabhakar wrote:
From: Marian-Cristian Rotariu
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Marian-Cristian Rotariu
Signed-off-by: Lad Prabhakar
Reviewed-by: Sergei Shtylyov
[...]
MBR, Sergei
On 08.08.2019 19:00, Christoph Hellwig wrote:
Ther is no need to go through dma_common_mmap for the arm-nommu
There. :-)
dma mmap implementation as the only possible memory not handled above
could be that from the per-device coherent pool.
Signed-off-by: Christoph Hellwig
[...]
MBR, S
Hello!
On 05.08.2019 11:01, Christoph Hellwig wrote:
Mips uses the KSEG1 kernel memory segment do map dma coherent
MIPS. s/do/to/?
allocations for n
on-coherent devices as uncachable, and does not have
Uncacheable?
any kind of special support for DMA_ATTR_WRITE_COMBINE in the al
Hello!
On 23.07.2019 8:26, Yoshihiro Shimoda wrote:
This patch adds a new dma_map_ops of get_merge_boundary() to
expose the DMA merge boundary if the domain type is IOMMU_DOMAIN_DMA.
Signed-off-by: Yoshihiro Shimoda
---
drivers/iommu/dma-iommu.c | 11 +++
1 file changed, 11 inserti
On 06/05/2019 02:11 PM, Yoshihiro Shimoda wrote:
> This patch adds a new capable IOMMU_CAP_MERGING to check whether
> the IOVA would be contiguous strictly if a device requires and
> the IOMMU driver has the capable.
s/has/is/? Or capable what?
> Signed-off-by: Yoshihiro Shimoda
> ---
> dri
Hello!
On 12/11/2018 04:43 PM, Joerg Roedel wrote:
> From: Joerg Roedel
>
> Some places in the kernel check the iommu_group pointer in
> 'struct device' in order to find ot whether a device is
> mapped by an IOMMU.
>
> This is not good way to make this check, as the pointer will
> be moved to
Hello!
On 10/15/2018 12:55 PM, Simon Horman wrote:
> From: Hai Nguyen Pham
>
> Support the r8a77990 IPMMU and update IPMMU_OF_DECLARE to hook up
That macro is gone, you need to update the description.
> the updated compat string.
>
> Signed-off-by: Hai Nguyen Pham
> Signed-off-by: Kazuya
On 10/31/2016 06:45 PM, Geert Uytterhoeven wrote:
If the system runs out of SW-IOMMU space, changes are high successive
s/changes/chances/?
requests will fail, too, flooding the kernel log. This is true
especially for streaming DMA, which is typically used repeatedly outside
the driver's
Hello.
On 6/7/2016 6:39 AM, Magnus Damm wrote:
From: Magnus Damm
Bump up the maximum numbers of micro-TLBS to 48.
Each IPMMU device instance get micro-TLB assignment via
the "iommus" property in DT. Older SoCs tend to use a
maximum number of 32 micro-TLBd per IPMMU instance however
Micr
Hello.
On 2/10/2016 3:57 AM, Niklas Söderlund wrote:
Add methods to handle mapping of device resources from a physical
address. This is needed for example to map be able to map MMIO FIFO
^^^ not needed
registers to a IOMMU.
Signed-off-by: Niklas Söde
Hello.
On 08/03/2015 04:25 PM, Will Deacon wrote:
A late change to the SMMUv3 architecture ensures that the OAS field
will be monotonically increasing, so we can assume that an unknown OAS
is at least 48-bit and use that, rather than fail the device probe.
Signed-off-by: Will Deacon
---
d
Hello.
On 3/6/2015 1:48 PM, yong...@mediatek.com wrote:
From: Yong Wu
This patch add smi binding document.
Signed-off-by: Yong Wu
---
.../devicetree/bindings/soc/mediatek/mediatek,smi.txt | 17 +
1 file changed, 17 insertions(+)
create mode 100644
Documentation/d
On 9/5/2014 3:33 PM, wangyijing wrote:
Use MSI chip framework instead of arch MSI functions to configure
MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework.
Signed-off-by: Yijing Wang
---
arch/powerpc/kernel/msi.c | 14 --
1 files changed, 12 insertions(+),
Hello.
On 9/5/2014 2:10 PM, Yijing Wang wrote:
Use MSI chip framework instead of arch MSI functions to configure
MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework.
Signed-off-by: Yijing Wang
---
arch/powerpc/kernel/msi.c | 14 --
1 files changed, 12 inser
Hello.
On 9/5/2014 2:09 PM, Yijing Wang wrote:
Use MSI chip framework instead of arch MSI functions to configure
MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework.
Signed-off-by: Yijing Wang
---
drivers/iommu/irq_remapping.c |8 +++-
1 files changed, 7 insertio
Hello.
On 04/21/2014 06:13 PM, Laurent Pinchart wrote:
The PTRS_PER_(PGD|PMD|PTE) macros evaluate to different values depending
on whether LPAE is enabled. The IPMMU driver uses a long descriptor
format regardless of LPAE, making those macros mismatch the IPMMU
configuration on non-LPAE systems
Hello.
On 03/29/2014 02:36 AM, Laurent Pinchart wrote:
Cc: devicet...@vger.kernel.org
Cc: Will Deacon
Signed-off-by: Laurent Pinchart
---
.../bindings/iommu/renesas,ipmmu-vmsa.txt | 35 ++
1 file changed, 35 insertions(+)
create mode 100644
Documentation/dev
Hello.
On 02/21/2014 08:16 PM, Will Deacon wrote:
From: Andreas Herrmann
This patch adds descriptions for new properties of the device tree
binding for the ARM SMMU architecture. These properties control
arm-smmu driver options.
Cc: Grant Likely
Acked-by: Rob Herring
Signed-off-by: And
Hello.
Marek Szyprowski wrote:
Fix registration to runtime pw and add missing resume callback.
Signed-off-by: Marek Szyprowski
Acked-by: Kyungmin Park
---
drivers/iommu/exynos-iommu.c | 20 ++--
1 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/io
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