> From: Lu Baolu
> Sent: Sunday, September 26, 2021 10:43 AM
>
> Hi Kevin,
>
> Thanks for reviewing my patch.
>
> On 9/24/21 11:16 AM, Tian, Kevin wrote:
> >> From: Lu Baolu
> >> Sent: Friday, September 24, 2021 10:30 AM
> >>
> >> The IOMMU VT-d implementation uses the first level for GPA->HPA
Hi Kevin,
Thanks for reviewing my patch.
On 9/24/21 11:16 AM, Tian, Kevin wrote:
From: Lu Baolu
Sent: Friday, September 24, 2021 10:30 AM
The IOMMU VT-d implementation uses the first level for GPA->HPA
translation
by default. Although both the first level and the second level could handle
the
Fenghua,
On Fri, Sep 24 2021 at 16:12, Fenghua Yu wrote:
> On Fri, Sep 24, 2021 at 03:18:12PM +0200, Thomas Gleixner wrote:
>> But OTOH why do you need a per task reference count on the PASID at all?
>>
>> The PASID is fundamentaly tied to the mm and the mm can't go away before
>> the threads hav
This patch makes iommu/amd call report_iommu_fault() when an I/O page
fault occurs, which has two effects:
1) It allows device drivers to register a callback to be notified of
I/O page faults, via the iommu_set_fault_handler() API.
2) It triggers the io_page_fault tracepoint in report_iommu_fa
On Sat, Aug 21, 2021 at 06:44:39PM +0300, Lennert Buytenhek wrote:
> > > - EVENT_FLAG_I unset, but the request was a translation request
> > > (EVENT_FLAG_TR set) or the target page was not present
> > > (EVENT_FLAG_PR unset): call report_iommu_fault(), but the RW
> > > bit will be invalid,