The IOMMU core has support for deferring the attachment of default domain
to device. Fix a missed deferred attaching check in iommu_probe_device().
Fixes: cf193888bfbd3 ("iommu: Move new probe_device path to separate function")
Cc: sta...@vger.kernel.org # v5.8+
Signed-off-by: Lu Baolu
---
drive
Hi Joerg,
Do you have any concerns regarding this patch?
Thanks,
Suravee
On 10/15/20 9:50 AM, Suravee Suthikulpanit wrote:
Certain device drivers allocate IO queues on a per-cpu basis.
On AMD EPYC platform, which can support up-to 256 cpu threads,
this can exceed the current MAX_IRQ_PER_TABLE
From: David Woodhouse
> Sent: 25 October 2020 10:26
> To: David Laight ; x...@kernel.org
>
> On Sun, 2020-10-25 at 09:49 +, David Laight wrote:
> > Just looking at a random one of these patches...
> >
> > Does the compiler manage to optimise that reasonably?
> > Or does it generate a lot of sh
On Sun, 2020-10-25 at 09:49 +, David Laight wrote:
> Just looking at a random one of these patches...
>
> Does the compiler manage to optimise that reasonably?
> Or does it generate a lot of shifts and masks as each
> bitfield is set?
>
> The code generation for bitfields is often a lot worse
From: David Woodhouse
> Sent: 24 October 2020 22:35
>
> From: Thomas Gleixner
>
> Use the msi_msg shadow structs and compose the message with named bitfields
> instead of the unreadable macro maze.
>
> Signed-off-by: Thomas Gleixner
> Signed-off-by: David Woodhouse
> ---
> arch/x86/pci/xen.c
Hi David,
nit: please use my kernel.org address for kernel related stuff.
On Sat, 24 Oct 2020 22:35:22 +0100,
David Woodhouse wrote:
>
> From: David Woodhouse
>
> Prerequesite to make x86 more irqdomain compliant.
Prerequisite?
>
> Signed-off-by: David Woodhouse
> Signed-off-by: Thomas Gl
On Sat, 2020-10-24 at 22:35 +0100, David Woodhouse wrote:
> Fix the conditions for enabling x2apic on guests without interrupt
> remapping, and support 15-bit Extended Destination ID to allow 32768
> CPUs without IR on hypervisors that support it.
>
> Make the I/OAPIC code generate its RTE direc
