Tomasz Nowicki writes:
> From: Marcin Wojtas
>
> Add IOMMU node for Marvell AP806 based SoCs together with platform
> and PCI device Stream ID mapping.
>
> Signed-off-by: Marcin Wojtas
> Signed-off-by: Tomasz Nowicki
Applied on mvebu/dt64
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell
Hello,
> czw., 16 lip 2020 o 14:02 Will Deacon napisaĆ(a):
>>
>> On Thu, Jul 16, 2020 at 01:00:43PM +0100, Will Deacon wrote:
>> > On Wed, 15 Jul 2020 09:06:45 +0200, Tomasz Nowicki wrote:
>> > > The series is meant to support SMMU for AP806 and a workaround
>> > > for accessing ARM SMMU 64bit re
Add global/context fault hooks to allow vendor specific implementations
override default fault interrupt handlers.
Update NVIDIA implementation to override the default global/context fault
interrupt handlers and handle interrupts across the two ARM MMU-500s that
are programmed identically.
Review
Add binding for NVIDIA's Tegra194 SoC SMMU.
Reviewed-by: Jon Hunter
Reviewed-by: Rob Herring
Reviewed-by: Robin Murphy
Signed-off-by: Krishna Reddy
---
.../devicetree/bindings/iommu/arm,smmu.yaml | 25 ++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/Documen
ioremap smmu mmio region before calling into implementation init.
This is necessary to allow mapped address available during vendor
specific implementation init.
Reviewed-by: Jon Hunter
Reviewed-by: Nicolin Chen
Reviewed-by: Pritesh Raithatha
Reviewed-by: Robin Murphy
Reviewed-by: Thierry Redi
Changes in v11:
Addressed Rob comment on DT binding patch to set min/maxItems of reg property
in else part.
Rebased on top of
https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/updates.
Changes in v10:
Perform SMMU base ioremap before calling implementation
Move TLB timeout and spin count macros to header file to
allow using the same from vendor specific implementations.
Reviewed-by: Jon Hunter
Reviewed-by: Nicolin Chen
Reviewed-by: Pritesh Raithatha
Reviewed-by: Robin Murphy
Reviewed-by: Thierry Reding
Signed-off-by: Krishna Reddy
---
drivers
NVIDIA's Tegra194 SoC has three ARM MMU-500 instances.
It uses two of the ARM MMU-500s together to interleave IOVA
accesses across them and must be programmed identically.
This implementation supports programming the two ARM MMU-500s
that must be programmed identically.
The third ARM MMU-500 insta
On Wed, Jul 08, 2020 at 05:24:47PM +0200, Christoph Hellwig wrote:
> Avoid the overhead of the dma ops support for tiny builds that only
> use the direct mapping.
>
> Signed-off-by: Christoph Hellwig
For ppc:pmac32_defconfig and other configurations, this patch results in:
Error log:
drivers/ma
Hi Yi,
On 7/12/20 1:21 PM, Liu Yi L wrote:
> From: Eric Auger
>
> The VFIO API was enhanced to support nested stage control: a bunch of
> new iotcls and usage guideline.
ioctls
>
> Let's document the process to follow to set up nested mode.
>
> Cc: Kevin Tian
> CC: Jacob Pan
> Cc: Alex Willi
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