Hi Jacob,
On 5/14/20 11:57 PM, Jacob Pan wrote:
+ /*
+* PASID table is per device for better security.
Therefore, for
+* each bind of a new device even with an existing PASID,
we need to
+* call the nested mode setup function here.
+*/
+ spin_lock(&iom
Hi Joerg,
> -Original Message-
> From: Joerg Roedel
> Sent: Thursday, May 14, 2020 12:56 PM
> To: Prakhya, Sai Praneeth
> Cc: iommu@lists.linux-foundation.org; Lu Baolu
> Subject: Re: [PATCH] iommu: Remove functions that support private domain
>
> On Thu, May 14, 2020 at 06:44:16PM +00
On Thu 27 Feb 18:57 PST 2020, Bjorn Andersson wrote:
Rob, Will, we're reaching the point where upstream has enough
functionality that this is becoming a critical issue for us.
E.g. Lenovo Yoga C630 is lacking this and a single dts patch to boot
mainline with display, GPU, WiFi and audio working a
13.05.2020 16:32, Marek Szyprowski пишет:
> The Documentation/DMA-API-HOWTO.txt states that the dma_map_sg() function
> returns the number of the created entries in the DMA address space.
> However the subsequent calls to the dma_sync_sg_for_{device,cpu}() and
> dma_unmap_sg must be called with the
On Thu, May 14, 2020 at 06:44:16PM +, Prakhya, Sai Praneeth wrote:
> Could you please explain why we shouldn't change default-domain for an
> iommu group that has multiple devices?
Because you can't be sure that a device is bound to a driver while the
default domain of the group is changed. As
On Thu May 14 20, Joerg Roedel wrote:
On Thu, May 14, 2020 at 05:36:23PM +0200, Joerg Roedel wrote:
This commit also removes the deferred attach of the device to its new
domain. Does the attached diff fix the problem for you?
+static int __iommu_attach_device_no_defer(struct iommu_domain *domain
From: Joerg Roedel
[ Upstream commit f44a4d7e4f1cdef73c90b1dc749c4d8a7372a8eb ]
The update_domain() function is expected to also inform the hardware
about domain changes. This needs a COMPLETION_WAIT command to be sent
to all IOMMUs which use the domain.
Signed-off-by: Joerg Roedel
Tested-by:
From: Joerg Roedel
[ Upstream commit eb791aa70b90c559eeb371d807c8813d569393f0 ]
The 'pt_root' and 'mode' struct members of 'struct protection_domain'
need to be get/set atomically, otherwise the page-table of the domain
can get corrupted.
Merge the fields into one atomic64_t struct member which
From: Joerg Roedel
[ Upstream commit 19c6978fba68a2cdedee7d55fb8c3063d47982d9 ]
The Device Table needs to be updated before the new page-table root
can be published in domain->pt_root. Otherwise a concurrent call to
fetch_pte might fetch a PTE which is not reachable through the Device
Table Entr
From: Joerg Roedel
[ Upstream commit 5b8a9a047b6cad361405c7900c1e1cdd378c4589 ]
When increase_address_space() fails to allocate memory, alloc_pte()
will call it again until it succeeds. Do not loop forever while trying
to increase the address space and just return an error instead.
Signed-off-b
From: Joerg Roedel
[ Upstream commit f44a4d7e4f1cdef73c90b1dc749c4d8a7372a8eb ]
The update_domain() function is expected to also inform the hardware
about domain changes. This needs a COMPLETION_WAIT command to be sent
to all IOMMUs which use the domain.
Signed-off-by: Joerg Roedel
Tested-by:
Hi Joerg,
> -Original Message-
> From: Joerg Roedel
> Sent: Thursday, May 14, 2020 11:33 AM
> To: Prakhya, Sai Praneeth
> Cc: iommu@lists.linux-foundation.org; Lu Baolu
> Subject: Re: [PATCH] iommu: Remove functions that support private domain
>
> On Thu, May 14, 2020 at 05:51:39PM +00
On Thu, May 14, 2020 at 05:51:39PM +, Prakhya, Sai Praneeth wrote:
> Sorry! didn't get that quite well. When you meant "per-group
> default-domain patch-set", do you mean the patch set that I am working
> on which changes iommu group default domain dynamically by writing to
> sysfs file?
Not o
Hi Joerg,
> -Original Message-
> From: Joerg Roedel
> Sent: Thursday, May 14, 2020 6:13 AM
> To: Prakhya, Sai Praneeth
> Cc: iommu@lists.linux-foundation.org; Lu Baolu
> Subject: Re: [PATCH] iommu: Remove functions that support private domain
>
> On Wed, May 13, 2020 at 03:47:21PM -070
Hi,
On Thu, May 14, 2020 at 03:16:47PM +0200, Joerg Roedel wrote:
> On Thu, May 14, 2020 at 03:09:00PM +0200, Maxime Ripard wrote:
> > On Thu, May 14, 2020 at 02:38:55PM +0200, Joerg Roedel wrote:
> > > On Wed, May 13, 2020 at 04:07:19PM +0200, Maxime Ripard wrote:
> > > > Maxime Ripard (5):
> > >
Hi Christoph,
Thanks a lot for the reviews, comments below.
Jacob
On Wed, 13 May 2020 22:59:30 -0700
Christoph Hellwig wrote:
> > + if (dev_is_pci(dev)) {
> > + /* VT-d supports devices with full 20 bit PASIDs
> > only */
> > + if (pci_max_pasids(to_pci_dev(dev)) != PASID
On Thu, May 14, 2020 at 05:36:23PM +0200, Joerg Roedel wrote:
> This commit also removes the deferred attach of the device to its new
> domain. Does the attached diff fix the problem for you?
> +static int __iommu_attach_device_no_defer(struct iommu_domain *domain,
> +
Hi Jerry,
On Wed, May 13, 2020 at 08:18:38PM -0700, Jerry Snitselaar wrote:
> We've seen kdump failures with recent kernels (5.5, 5.6, 5.7-rc1) on
> amd systems when iommu is enabled in translation mode. In the cases so
> far there has been mpt3sas involved, but I'm also seeing io page
> faults fo
On Wed, 13 May 2020 22:54:24 -0700
Christoph Hellwig wrote:
> > +* 1. CPU vs. IOMMU
> > +* 2. Guest vs. Host.
> > +*/
> > + switch (addr_width) {
> > +#ifdef CONFIG_X86
> > + case ADDR_WIDTH_5LEVEL:
> > + if (cpu_feature_enabled(X86_FEATURE_LA57) &&
> > + c
On Thu 14 May 07:39 PDT 2020, Shawn Guo wrote:
> Hi Bjorn,
>
> On Mon, May 11, 2020 at 10:52:42PM -0700, Bjorn Andersson wrote:
> > On Sat 09 May 06:08 PDT 2020, Shawn Guo wrote:
> >
> > > On some SoCs like MSM8939 with A405 adreno, there is a gfx_tbu clock
> > > needs to be on while doing TLB i
On Wed, 13 May 2020 22:51:32 -0700
Christoph Hellwig wrote:
> On Wed, May 13, 2020 at 04:01:43PM -0700, Jacob Pan wrote:
> > An Intel iommu domain uses 5-level page table by default. If the
> > iommu that the domain tries to attach supports less page levels,
> > the top level page tables should b
Hi Bjorn,
On Mon, May 11, 2020 at 10:52:42PM -0700, Bjorn Andersson wrote:
> On Sat 09 May 06:08 PDT 2020, Shawn Guo wrote:
>
> > On some SoCs like MSM8939 with A405 adreno, there is a gfx_tbu clock
> > needs to be on while doing TLB invalidate. Otherwise, TLBSYNC status
> > will not be correctly
On Wed, May 13, 2020 at 8:33 AM Marek Szyprowski
wrote:
>
> The Documentation/DMA-API-HOWTO.txt states that the dma_map_sg() function
> returns the number of the created entries in the DMA address space.
> However the subsequent calls to the dma_sync_sg_for_{device,cpu}() and
> dma_unmap_sg must b
On Thu, May 14, 2020 at 03:09:00PM +0200, Maxime Ripard wrote:
> On Thu, May 14, 2020 at 02:38:55PM +0200, Joerg Roedel wrote:
> > On Wed, May 13, 2020 at 04:07:19PM +0200, Maxime Ripard wrote:
> > > Maxime Ripard (5):
> > > dt-bindings: iommu: Add Allwinner H6 IOMMU bindings
> > > dt-bindings:
On Wed, May 13, 2020 at 03:47:21PM -0700, Sai Praneeth Prakhya wrote:
> After moving iommu_group setup to iommu core code [1][2] and removing
> private domain support in vt-d [3], there are no users for functions such
> as iommu_request_dm_for_dev(), iommu_request_dma_domain_for_dev() and
> request
On Thu, May 14, 2020 at 02:38:55PM +0200, Joerg Roedel wrote:
> On Wed, May 13, 2020 at 04:07:19PM +0200, Maxime Ripard wrote:
> > Maxime Ripard (5):
> > dt-bindings: iommu: Add Allwinner H6 IOMMU bindings
> > dt-bindings: display: sun8i-mixer: Allow for an iommu property
> > iommu: Add Allwi
From: Joerg Roedel
Allocate zeroed memory so there is no need to memset it to 0 in the
driver.
Cc: Maxime Ripard
Signed-off-by: Joerg Roedel
---
drivers/iommu/sun50i-iommu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun5
From: Joerg Roedel
A few compile warnings show up when building this driver:
CC drivers/iommu/sun50i-iommu.o
drivers/iommu/sun50i-iommu.c: In function ‘sun50i_dte_get_page_table’:
drivers/iommu/sun50i-iommu.c:486:16: warning: unused variable ‘flags’
[-Wunused-variable]
486 | unsigned
On Wed, May 13, 2020 at 04:07:19PM +0200, Maxime Ripard wrote:
> Maxime Ripard (5):
> dt-bindings: iommu: Add Allwinner H6 IOMMU bindings
> dt-bindings: display: sun8i-mixer: Allow for an iommu property
> iommu: Add Allwinner H6 IOMMU driver
> arm64: dts: allwinner: h6: Add IOMMU
> drm/su
On Wed, May 13, 2020 at 11:16:14PM +0100, Guillaume Tucker wrote:
> which this time gave me:
>
> <4>[2.540558] PC is at iommu_probe_device+0x1c/0x15c
> <4>[2.545606] LR is at of_iommu_configure+0x15c/0x1c4
> <4>[2.550736] pc : []lr : []psr: a013
>
> which in turn brings us
On Thu, May 14, 2020 at 12:50:16PM +0200, Jean-Philippe Brucker wrote:
> On Thu, May 14, 2020 at 05:31:00AM -0400, Michael S. Tsirkin wrote:
> > On Thu, May 14, 2020 at 01:22:37PM +0530, Bharat Bhushan wrote:
> > > Different endpoint can support different page size, probe
> > > endpoint if it suppo
On Thu, May 14, 2020 at 05:31:00AM -0400, Michael S. Tsirkin wrote:
> On Thu, May 14, 2020 at 01:22:37PM +0530, Bharat Bhushan wrote:
> > Different endpoint can support different page size, probe
> > endpoint if it supports specific page size otherwise use
> > global page sizes.
> >
> > Device att
On Thu, May 14, 2020 at 01:22:37PM +0530, Bharat Bhushan wrote:
> Different endpoint can support different page size, probe
> endpoint if it supports specific page size otherwise use
> global page sizes.
>
> Device attached to domain should support a minimum of
> domain supported page sizes. If de
Different endpoint can support different page size, probe
endpoint if it supports specific page size otherwise use
global page sizes.
Device attached to domain should support a minimum of
domain supported page sizes. If device supports more
than domain supported page sizes then device is limited
t
Different endpoint can support different page size, probe
endpoint if it supports specific page size otherwise use
global page sizes.
Device attached to domain should support a minimum of
domain supported page sizes. If device supports more
than domain supported page sizes then device is limited
t
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