[PATCH v4 5/8] iommu/vt-d: Return ID associated with an auxiliary domain

This adds support to return the default pasid associated with an auxiliary domain. The PCI device which is bound with this domain should use this value as the pasid for all DMA requests of the subset of device which is isolated and protected with this domain. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevi

[PATCH v4 7/8] vfio/type1: Add domain at(de)taching group helpers

This adds helpers to attach or detach a domain to a group. This will replace iommu_attach_group() which only works for pci devices. If a domain is attaching to a group which includes the mediated devices, it should attach to the iommu device (a pci device which represents the mdev in iommu scope)

[PATCH v4 4/8] iommu/vt-d: Attach/detach domains in auxiliary mode

When multiple domains per device has been enabled by the device driver, the device will tag the default PASID for the domain to all DMA traffics out of the subset of this device; and the IOMMU should translate the DMA requests in PASID granularity. This extends the intel_iommu_attach/detach_device

[PATCH v4 6/8] vfio/mdev: Add iommu place holders in mdev_device

A parent device might create different types of mediated devices. For example, a mediated device could be created by the parent device with full isolation and protection provided by the IOMMU. One usage case could be found on Intel platforms where a mediated device is an assignable subset of a PCI,

[PATCH v4 8/8] vfio/type1: Handle different mdev isolation type

This adds the support to determine the isolation type of a mediated device group by checking whether it has an iommu device. If an iommu device exists, an iommu domain will be allocated and then attached to the iommu device. Otherwise, keep the same behavior as it is. Cc: Ashok Raj Cc: Jacob Pan

[PATCH v4 3/8] iommu/vt-d: Enable/disable multiple domains per device

Add iommu ops for enabling and disabling multiple domains per device. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Signed-off-by: Lu Baolu Signed-off-by: Liu Yi L --- drivers/iommu/intel-iommu.c | 65 - include/linux/intel-iommu.h | 1 + 2 files changed, 65

[PATCH v4 1/8] iommu: Add APIs for multiple domains per device

Sharing a physical PCI device in a finer-granularity way is becoming a consensus in the industry. IOMMU vendors are also engaging efforts to support such sharing as well as possible. Among the efforts, the capability of support finer-granularity DMA isolation is a common requirement due to the secu

[PATCH v4 2/8] iommu/vt-d: Add multiple domains per device query

Add the response to IOMMU_DEV_ATTR_AUXD_CAPABILITY capability query through iommu_get_dev_attr(). Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Signed-off-by: Lu Baolu Signed-off-by: Liu Yi L --- drivers/iommu/intel-iommu.c | 38 + 1 file changed, 38 insertio

[PATCH v4 0/8] vfio/mdev: IOMMU aware mediated device

Hi, The Mediate Device is a framework for fine-grained physical device sharing across the isolated domains. Currently the mdev framework is designed to be independent of the platform IOMMU support. As the result, the DMA isolation relies on the mdev parent device in a vendor specific way. There a

Re: [PATCH v4 11/12] iommu/vt-d: Shared virtual address in scalable mode

Hi, On 11/5/18 3:15 PM, Christoph Hellwig wrote: --- a/include/linux/dma_remapping.h +++ b/include/linux/dma_remapping.h FYI, this file seems to be entirely VT-D specific, but has an awfully generic name. It should be renamed to something more suitable (or maybe just merged into intel-iommu.h

Re: [PATCH v4 11/12] iommu/vt-d: Shared virtual address in scalable mode

> --- a/include/linux/dma_remapping.h > +++ b/include/linux/dma_remapping.h FYI, this file seems to be entirely VT-D specific, but has an awfully generic name. It should be renamed to something more suitable (or maybe just merged into intel-iommu.h?) and also grow some comments describing the con

RE: [PATCH 1/1] iommu/vtd: Fix NULL pointer dereference in prq_event_thread()

> From: Lu Baolu [mailto:baolu...@linux.intel.com] > Sent: Monday, November 5, 2018 1:45 PM > To: Liu, Yi L ; Joerg Roedel ; David > Woodhouse > Cc: baolu...@linux.intel.com; Raj, Ashok ; linux- > ker...@vger.kernel.org; iommu@lists.linux-foundation.org > Subject: Re: [PATCH 1/1] iommu/vtd: Fix NU

Re: [PATCH 1/1] iommu/vtd: Fix NULL pointer dereference in prq_event_thread()

Hi Yi, On 11/5/18 1:21 PM, Liu, Yi L wrote: Hi Baolu, From: iommu-boun...@lists.linux-foundation.org [mailto:iommu- boun...@lists.linux-foundation.org] On Behalf Of Lu Baolu Sent: Monday, November 5, 2018 10:19 AM To: Joerg Roedel ; David Woodhouse Cc: Raj, Ashok ; linux-ker...@vger.kernel.or

[PATCH v4 12/12] iommu/vt-d: Remove deferred invalidation

Deferred invalidation is an ECS specific feature. It will not be supported when IOMMU works in scalable mode. As we deprecated the ECS support, remove deferred invalidation and cleanup the code. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Cc: Liu Yi L Signed-off-by: Lu Baolu Reviewed-by: Ashok

[PATCH v4 08/12] iommu/vt-d: Pass pasid table to context mapping

So that the pasid related info, such as the pasid table and the maximum of pasid could be used during setting up scalable mode context. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Cc: Liu Yi L Signed-off-by: Lu Baolu Reviewed-by: Ashok Raj Reviewed-by: Kevin Tian --- drivers/iommu/intel-iom

[PATCH v4 07/12] iommu/vt-d: Setup pasid entry for RID2PASID support

when the scalable mode is enabled, there is no second level page translation pointer in the context entry any more (for DMA request without PASID). Instead, a new RID2PASID field is introduced in the context entry. Software can choose any PASID value to set RID2PASID and then setup the translation

[PATCH v4 11/12] iommu/vt-d: Shared virtual address in scalable mode

This patch enables the current SVA (Shared Virtual Address) implementation to work in the scalable mode. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Cc: Liu Yi L Signed-off-by: Sanjay Kumar Signed-off-by: Lu Baolu Reviewed-by: Ashok Raj --- drivers/iommu/intel-iommu.c | 38 ---

[PATCH v4 10/12] iommu/vt-d: Add first level page table interface

This adds an interface to setup the PASID entries for first level page table translation. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Cc: Liu Yi L Signed-off-by: Sanjay Kumar Signed-off-by: Lu Baolu Reviewed-by: Ashok Raj --- drivers/iommu/intel-pasid.c | 81

[PATCH v4 09/12] iommu/vt-d: Setup context and enable RID2PASID support

This patch enables the translation for requests without PASID in the scalable mode by setting up the root and context entries. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Cc: Liu Yi L Signed-off-by: Sanjay Kumar Signed-off-by: Lu Baolu Reviewed-by: Ashok Raj --- drivers/iommu/intel-iommu.c

[PATCH v4 04/12] iommu/vt-d: Add 256-bit invalidation descriptor support

Intel vt-d spec rev3.0 requires software to use 256-bit descriptors in invalidation queue. As the spec reads in section 6.5.2: Remapping hardware supporting Scalable Mode Translations (ECAP_REG.SMTS=1) allow software to additionally program the width of the descriptors (128-bits or 256-bits) that

[PATCH v4 00/12] iommu/vt-d: Add scalable mode support

Hi, Intel vt-d rev3.0 [1] introduces a new translation mode called 'scalable mode', which enables PASID-granular translations for first level, second level, nested and pass-through modes. The vt-d scalable mode is the key ingredient to enable Scalable I/O Virtualization (Scalable IOV) [2] [3], whi

[PATCH v4 05/12] iommu/vt-d: Reserve a domain id for FL and PT modes

Vt-d spec rev3.0 (section 6.2.3.1) requires that each pasid entry for first-level or pass-through translation should be programmed with a domain id different from those used for second-level or nested translation. It is recommended that software could use a same domain id for all first-only and pas

[PATCH v4 02/12] iommu/vt-d: Manage scalalble mode PASID tables

In scalable mode, pasid structure is a two level table with a pasid directory table and a pasid table. Any pasid entry can be identified by a pasid value in below way. 1 9 6 5 0 .---.---. | PASID| | '--

[PATCH v4 06/12] iommu/vt-d: Add second level page table interface

This adds the interfaces to setup or tear down the structures for second level page table translations. This includes types of second level only translation and pass through. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Cc: Liu Yi L Signed-off-by: Sanjay Kumar Signed-off-by: Lu Baolu Reviewed-

[PATCH v4 01/12] iommu/vt-d: Enumerate the scalable mode capability

The Intel vt-d spec rev3.0 introduces a new translation mode called scalable mode, which enables PASID-granular translations for first level, second level, nested and pass-through modes. At the same time, the previous Extended Context (ECS) mode is deprecated (no production ever implements ECS). T

[PATCH v4 03/12] iommu/vt-d: Move page table helpers into header

So that they could also be used in other source files. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Cc: Liu Yi L Signed-off-by: Lu Baolu Reviewed-by: Ashok Raj Reviewed-by: Kevin Tian --- drivers/iommu/intel-iommu.c | 43 - include/linux/intel-iommu.h | 43

RE: [PATCH 1/1] iommu/vtd: Fix NULL pointer dereference in prq_event_thread()

Hi Baolu, > From: iommu-boun...@lists.linux-foundation.org [mailto:iommu- > boun...@lists.linux-foundation.org] On Behalf Of Lu Baolu > Sent: Monday, November 5, 2018 10:19 AM > To: Joerg Roedel ; David Woodhouse > Cc: Raj, Ashok ; linux-ker...@vger.kernel.org; > iommu@lists.linux-foundation.org

[PATCH 1/1] iommu/vtd: Fix NULL pointer dereference in prq_event_thread()

When handling page request without pasid event, go to "no_pasid" branch instead of "bad_req". Otherwise, a NULL pointer deference will happen there. Cc: Ashok Raj Cc: Jacob Pan Cc: Sohil Mehta Signed-off-by: Lu Baolu --- drivers/iommu/intel-svm.c | 2 +- 1 file changed, 1 insertion(+), 1 dele

Re: [PATCH] iommu/dma: Zero pages manually in a length of scatterlist

On Thu, Nov 01, 2018 at 02:35:00PM -0700, Nicolin Chen wrote: > The __GFP_ZERO will be passed down to the generic page allocation > routine which zeros everything page by page. This is safe to be a > generic way but not efficient for iommu allocation that organizes > contiguous pages using scatterl