Hi Rob,
On Thu, Aug 30, 2018 at 8:16 PM Vivek Gautam
wrote:
>
> Add bindings doc for Qcom's smmu-v2 implementation.
>
> Signed-off-by: Vivek Gautam
> Reviewed-by: Tomasz Figa
> Tested-by: Srinivas Kandagatla
> ---
I removed your reviewed-by for this particular patch.
Can you please consider g
> From: Lu Baolu [mailto:baolu...@linux.intel.com]
> Sent: Thursday, August 30, 2018 9:35 AM
>
> So that the pasid related info, such as the pasid table and the
> maximum of pasid could be used during setting up scalable mode
> context.
>
> Cc: Ashok Raj
> Cc: Jacob Pan
> Cc: Kevin Tian
> Cc:
> From: Lu Baolu [mailto:baolu...@linux.intel.com]
> Sent: Thursday, August 30, 2018 9:35 AM
>
> This adds the interfaces to setup or tear down the structures
> for second level page table translations. This includes types
> of second level only translation and pass through.
>
> Cc: Ashok Raj
>
Hi,
On 09/06/2018 10:52 AM, Tian, Kevin wrote:
From: Lu Baolu [mailto:baolu...@linux.intel.com]
Sent: Thursday, September 6, 2018 10:46 AM
[...]
@@ -143,8 +142,9 @@ int intel_pasid_alloc_table(struct device *dev)
return -ENOMEM;
INIT_LIST_HEAD(&pasid_table->dev);
-
> From: Lu Baolu [mailto:baolu...@linux.intel.com]
> Sent: Thursday, September 6, 2018 10:46 AM
>
[...]
> >> @@ -143,8 +142,9 @@ int intel_pasid_alloc_table(struct device *dev)
> >>return -ENOMEM;
> >>INIT_LIST_HEAD(&pasid_table->dev);
> >>
> >> - size = sizeof(struct pasid_entry)
Hi,
On 09/06/2018 10:15 AM, Tian, Kevin wrote:
From: Lu Baolu [mailto:baolu...@linux.intel.com]
Sent: Thursday, August 30, 2018 9:35 AM
So that they could also be used in other source files.
Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Cc: Liu Yi L
Signed-off-by: Lu Baolu
Reviewed-by: Ashok
Hi,
On 09/06/2018 10:14 AM, Tian, Kevin wrote:
From: Lu Baolu [mailto:baolu...@linux.intel.com]
Sent: Thursday, August 30, 2018 9:35 AM
In scalable mode, pasid structure is a two level table with
a pasid directory table and a pasid table. Any pasid entry
can be identified by a pasid value in be
> From: Lu Baolu [mailto:baolu...@linux.intel.com]
> Sent: Thursday, August 30, 2018 9:35 AM
>
> Intel vt-d spec rev3.0 requires software to use 256-bit
> descriptors in invalidation queue. As the spec reads in
> section 6.5.2:
>
> Remapping hardware supporting Scalable Mode Translations
> (ECAP_
Hi,
On 09/06/2018 09:55 AM, Tian, Kevin wrote:
From: Lu Baolu [mailto:baolu...@linux.intel.com]
Sent: Thursday, August 30, 2018 9:35 AM
The Intel vt-d spec rev3.0 introduces a new translation
mode called scalable mode, which enables PASID-granular
translations for first level, second level, nes
> From: Lu Baolu [mailto:baolu...@linux.intel.com]
> Sent: Thursday, August 30, 2018 9:35 AM
>
> So that they could also be used in other source files.
>
> Cc: Ashok Raj
> Cc: Jacob Pan
> Cc: Kevin Tian
> Cc: Liu Yi L
> Signed-off-by: Lu Baolu
> Reviewed-by: Ashok Raj
Reviewed-by: Kevin Ti
> From: Lu Baolu [mailto:baolu...@linux.intel.com]
> Sent: Thursday, August 30, 2018 9:35 AM
>
> In scalable mode, pasid structure is a two level table with
> a pasid directory table and a pasid table. Any pasid entry
> can be identified by a pasid value in below way.
>
>1
>9
> From: Lu Baolu [mailto:baolu...@linux.intel.com]
> Sent: Thursday, August 30, 2018 9:35 AM
>
> The Intel vt-d spec rev3.0 introduces a new translation
> mode called scalable mode, which enables PASID-granular
> translations for first level, second level, nested and
> pass-through modes. At the s
Hi,
On 09/06/2018 03:15 AM, Alex Williamson wrote:
On Wed, 5 Sep 2018 03:01:39 +
"Tian, Kevin" wrote:
From: Lu Baolu [mailto:baolu...@linux.intel.com]
Sent: Thursday, August 30, 2018 12:09 PM
[...]
In order to distinguish the IOMMU-capable mediated devices from those
which still ne
Hi,
On 09/06/2018 03:37 AM, Alex Williamson wrote:
On Thu, 30 Aug 2018 12:09:15 +0800
Lu Baolu wrote:
Otherwise, there will be a build warning:
drivers/iommu/amd_iommu.c:3083:2: warning: enumeration value
'IOMMU_CAP_AUX_DOMAIN' not handled in switch [-Wswitch]
There is no functional change.
Hi,
On 09/06/2018 03:35 AM, Alex Williamson wrote:
On Thu, 30 Aug 2018 12:09:14 +0800
Lu Baolu wrote:
Add the response to IOMMU_CAP_AUX_DOMAIN capability query
through iommu_capable(). Return true if IOMMUs support the
scalable mode, return false otherwise.
Cc: Ashok Raj
Cc: Jacob Pan
Cc:
Use the for_each_of_cpu_node iterator to iterate over cpu nodes. This
has the side effect of defaulting to iterating using "cpu" node names in
preference to the deprecated (for FDT) device_type == "cpu".
Cc: Joerg Roedel
Cc: iommu@lists.linux-foundation.org
Signed-off-by: Rob Herring
---
Please
This series adds an iterator for cpu nodes and converts users over to use
it or of_get_cpu_node in some cases. This allows us to remove the
dependency on device_type property for cpu nodes though removing that
from DTS files will have to wait for some time. In some cases, this makes
the DT search m
On Thu, 30 Aug 2018 12:09:15 +0800
Lu Baolu wrote:
> Otherwise, there will be a build warning:
>
> drivers/iommu/amd_iommu.c:3083:2: warning: enumeration value
> 'IOMMU_CAP_AUX_DOMAIN' not handled in switch [-Wswitch]
>
> There is no functional change.
>
> Signed-off-by: Lu Baolu
> ---
> dri
On Thu, 30 Aug 2018 12:09:14 +0800
Lu Baolu wrote:
> Add the response to IOMMU_CAP_AUX_DOMAIN capability query
> through iommu_capable(). Return true if IOMMUs support the
> scalable mode, return false otherwise.
>
> Cc: Ashok Raj
> Cc: Jacob Pan
> Cc: Kevin Tian
> Cc: Liu Yi L
> Signed-off-
On Wed, 5 Sep 2018 03:01:39 +
"Tian, Kevin" wrote:
> > From: Lu Baolu [mailto:baolu...@linux.intel.com]
> > Sent: Thursday, August 30, 2018 12:09 PM
> >
> [...]
> >
> > In order to distinguish the IOMMU-capable mediated devices from those
> > which still need to rely on parent devices, th
On Wed, 5 Sep 2018 14:14:12 +0200
Auger Eric wrote:
> > + *
> > + * On Arm and AMD IOMMUs, entry 0 of the PASID table can be used
> > to hold
> > + * non-PASID translations. In this case PASID 0 is reserved and
> > entry 0 points
> > + * to the io_pgtable base. On Intel IOMMU, the io_pgtable base
在 2018年09月05日 14:46, Dave Young 写道:
> [snip]
>>
>> As previously mentioned, there are also many differences between kexec and
>> kdump. In general,
>> kexec needs to look at all of available physical memory, but kdump doesn't
>> need.
>>
>> For kexec, kexec-tools will read /sys/firmware/memmap an
Hi Jean-Philippe,
On 05/11/2018 09:06 PM, Jean-Philippe Brucker wrote:
> When an mm exits, devices that were bound to it must stop performing DMA
> on its PASID. Let device drivers register a callback to be notified on mm
> exit. Add the callback to the sva_param structure attached to struct
> dev
Hi Jean-Philippe,
On 05/11/2018 09:06 PM, Jean-Philippe Brucker wrote:
> Allocate IOMMU mm structures and binding them to devices. Four operations
s/binding/bind
> are added to IOMMU drivers:
>
> * mm_alloc(): to create an io_mm structure and perform architecture-
> specific operations required
Hi Jean-Philippe,
On 05/11/2018 09:06 PM, Jean-Philippe Brucker wrote:
> Add bind() and unbind() operations to the IOMMU API. Bind() returns a
> PASID that drivers can program in hardware, to let their devices access an
> mm. This patch only adds skeletons for the device driver API, most of the
>
Hi Jean-Philippe,
On 05/11/2018 09:06 PM, Jean-Philippe Brucker wrote:
> Shared Virtual Addressing (SVA) provides a way for device drivers to bind
> process address spaces to devices. This requires the IOMMU to support page
> table format and features compatible with the CPUs, and usually requires
On 9/5/2018 3:34 PM, Rob Clark wrote:
On Wed, Sep 5, 2018 at 5:22 AM Vivek Gautam wrote:
On 8/14/2018 5:54 PM, Vivek Gautam wrote:
Hi Will,
On 8/14/2018 5:10 PM, Will Deacon wrote:
Hi Vivek,
On Tue, Aug 14, 2018 at 04:25:23PM +0530, Vivek Gautam wrote:
Qcom's implementation of arm,mmu
On 05/09/2018 04:15, Xu Zaibo wrote:
>>> 1. While the series are finished well, VFIO-PCI device can be held
>>> by only one process
>>> through binding IOCTL command without PASID (without PASID
>>> being exposed user space).
>> It could, but isn't supported at the moment. In additi
On Wed, Sep 5, 2018 at 5:22 AM Vivek Gautam wrote:
>
>
> On 8/14/2018 5:54 PM, Vivek Gautam wrote:
> > Hi Will,
> >
> >
> > On 8/14/2018 5:10 PM, Will Deacon wrote:
> >> Hi Vivek,
> >>
> >> On Tue, Aug 14, 2018 at 04:25:23PM +0530, Vivek Gautam wrote:
> >>> Qcom's implementation of arm,mmu-500 on
On 8/14/2018 5:54 PM, Vivek Gautam wrote:
Hi Will,
On 8/14/2018 5:10 PM, Will Deacon wrote:
Hi Vivek,
On Tue, Aug 14, 2018 at 04:25:23PM +0530, Vivek Gautam wrote:
Qcom's implementation of arm,mmu-500 on sdm845 has a
functional/performance
errata [1] because of which the TCU cache look up
Hi Kenneth,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on cryptodev/master]
[also build test WARNING on v4.19-rc2 next-20180905]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com
31 matches
Mail list logo
