Difference between IOVA and bus address when SMMU is enabled

Hi All, What is the difference between IOVA address and bus address when SMMU is enabled ? Is IOVA address term used only when hypervisor is present ? Regards, Valmiki --- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus

Re: [PATCH v3 3/3] arm64: Force swiotlb bounce buffering for non-coherent DMA with large CWG

On Fri, May 11, 2018 at 02:55:47PM +0100, Catalin Marinas wrote: > On systems with a Cache Writeback Granule (CTR_EL0.CWG) greater than > ARCH_DMA_MINALIGN, DMA cache maintenance on sub-CWG ranges is not safe, > leading to data corruption. If such configuration is detected, the > kernel will force

Re: [PATCH] swiotlb: Silent unwanted warning "buffer is full"

Thanks. I manually applied this for 4.17-rc, as the mail unfortunately was garbled. ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu