On Fri, 23 Jun 2017 14:34:34 -0600
Alex Williamson wrote:
> > for_each_pci_dev(dev) {
> <-- look in here, it's trickier than it
> appears
you are right, thanks.
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On Fri, 23 Jun 2017 13:16:29 -0700
Jacob Pan wrote:
> On Thu, 22 Jun 2017 16:53:58 -0600
> Alex Williamson wrote:
>
> > On Wed, 14 Jun 2017 15:23:02 -0700
> > Jacob Pan wrote:
> >
> > > If the source device of a page request has its PASID table pointer
> > > bond to a guest, the first level
On Fri, 23 Jun 2017 12:59:00 -0600
Alex Williamson wrote:
> On Fri, 23 Jun 2017 11:19:52 -0700
> Jacob Pan wrote:
>
> > On Thu, 22 Jun 2017 16:52:15 -0600
> > Alex Williamson wrote:
> >
> > > On Wed, 14 Jun 2017 15:22:56 -0700
> > > Jacob Pan wrote:
> > > > +static int intel_iommu_unbind
On Thu, 22 Jun 2017 16:54:16 -0600
Alex Williamson wrote:
> On Wed, 14 Jun 2017 15:23:01 -0700
> Jacob Pan wrote:
>
> > Currently, when device DMA faults are detected by IOMMU the fault
> > reasons are printed but the offending device is not notified.
> > This patch allows device drivers to be
On Thu, 22 Jun 2017 16:53:58 -0600
Alex Williamson wrote:
> On Wed, 14 Jun 2017 15:23:02 -0700
> Jacob Pan wrote:
>
> > If the source device of a page request has its PASID table pointer
> > bond to a guest, the first level page tables are owned by the guest.
> > In this case, we shall let gues
On Fri, 23 Jun 2017 11:59:28 -0700
Jacob Pan wrote:
> On Thu, 22 Jun 2017 16:53:17 -0600
> Alex Williamson wrote:
>
> > On Wed, 14 Jun 2017 15:22:59 -0700
> > Jacob Pan wrote:
> >
> > > Traditionally, device specific faults are detected and handled
> > > within their own device drivers. Whe
On Fri, 23 Jun 2017 11:19:52 -0700
Jacob Pan wrote:
> On Thu, 22 Jun 2017 16:52:15 -0600
> Alex Williamson wrote:
>
> > On Wed, 14 Jun 2017 15:22:56 -0700
> > Jacob Pan wrote:
> > > +static int intel_iommu_unbind_pasid_table(struct iommu_domain
> > > *domain,
> > > +
On Thu, 22 Jun 2017 16:53:17 -0600
Alex Williamson wrote:
> On Wed, 14 Jun 2017 15:22:59 -0700
> Jacob Pan wrote:
>
> > Traditionally, device specific faults are detected and handled
> > within their own device drivers. When IOMMU is enabled, faults such
> > as DMA related transactions are dete
On Thu, 22 Jun 2017 16:52:01 -0600
Alex Williamson wrote:
> On Wed, 14 Jun 2017 15:22:55 -0700
> Jacob Pan wrote:
>
> > Virtual IOMMU was proposed to support Shared Virtual Memory (SVM)
> > use case in the guest:
> > https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg05311.html
> >
> > A
On Thu, 22 Jun 2017 16:52:15 -0600
Alex Williamson wrote:
> On Wed, 14 Jun 2017 15:22:56 -0700
> Jacob Pan wrote:
>
> > Add Intel VT-d ops to the generic iommu_bind_pasid_table API
> > functions.
> >
> > The primary use case is for direct assignment of SVM capable
> > device. Originated from e
On 6/23/2017 5:00 AM, Borislav Petkov wrote:
On Fri, Jun 16, 2017 at 01:56:19PM -0500, Tom Lendacky wrote:
Add the support to encrypt the kernel in-place. This is done by creating
new page mappings for the kernel - a decrypted write-protected mapping
and an encrypted mapping. The kernel is encry
On Fri, Jun 16, 2017 at 01:56:39PM -0500, Tom Lendacky wrote:
> Add support to check if SME has been enabled and if memory encryption
> should be activated (checking of command line option based on the
> configuration of the default state). If memory encryption is to be
> activated, then the encry
On Fri, Jun 23, 2017 at 03:58:00PM +0100, shameer wrote:
> The helper function retrieves ITS address regions through IORT
> device <-> ITS mappings and reserves it so that these regions
> will not be translated by IOMMU and will be excluded from IOVA
> allocations. IOMMU drivers can use this to imp
On 06/23/2017 03:39 PM, Sinan Kaya wrote:
> Hi Jean-Philippe,
>
>> On 2/27/2017 2:54 PM, Jean-Philippe Brucker wrote:
>> Enable PASID for PCI devices that support it.
>>
>> Signed-off-by: Jean-Philippe Brucker
>> ---
>> drivers/iommu/arm-smmu-v3.c | 66
>> ++
The helper function retrieves ITS address regions through IORT
device <-> ITS mappings and reserves it so that these regions
will not be translated by IOMMU and will be excluded from IOVA
allocations. IOMMU drivers can use this to implement their
.get_resv_regions callback.
Signed-off-by: shameer
On certain HiSilicon platforms (Hip06/Hip07) the GIC ITS and
PCIe RC deviates from the standard implementation and this breaks
PCIe MSI functionality when SMMU is enabled.
The HiSilicon erratum 161010801 describes this limitation of certain
HiSilicon platforms to support the SMMU mappings for MSI
The HiSilicon erratum 161010801 describes the limitation of HiSilicon
platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions.
On these platforms GICv3 ITS translator is presented with the deviceID
by extending the MSI payload data to 64 bits to include the deviceID.
Hence, the PCI
Hi Jean-Philippe,
> On 2/27/2017 2:54 PM, Jean-Philippe Brucker wrote:
> Enable PASID for PCI devices that support it.
>
> Signed-off-by: Jean-Philippe Brucker
> ---
> drivers/iommu/arm-smmu-v3.c | 66
> ++---
> 1 file changed, 63 insertions(+), 3 deleti
On Thu, 2017-06-22 at 23:57 +0200, Joerg Roedel wrote:
> On Thu, Jun 22, 2017 at 11:13:09AM -0400, Jan Vesely wrote:
> > It looks like I tested different patches.
> > linux-4.10.17 with both
> > "iommu/amd: Optimize iova queue flushing"
>
> This patch isn't in my tree and will not go upstream.
>
From: Geetha Sowjanya
Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq
lines for gerror, eventq and cmdq-sync.
New named irq "combined" is set as a errata workaround, which allows to
share the irq line by register single irq handler for all the interrupts.
Signed-off-b
On Fri, Jun 16, 2017 at 01:56:30PM -0500, Tom Lendacky wrote:
> Add a cmdline_find_option() function to look for cmdline options that
> take arguments. The argument is returned in a supplied buffer and the
> argument length (regardless of whether it fits in the supplied buffer)
> is returned, with
Pass-through devices to VM guest can get updated affinity
information via irq_set_affinity(). Currently, AMD IOMMU driver
in GA mode ignores the updated information if the pass-through
device is setup to use vAPIC, which could cause invalid interrupt
remapping when not running in guest_mode.
Also,
Hi Joerg,
On 06/23/17 at 04:57pm, Baoquan He wrote:
> Hi dear Joerg,
>
> On 06/16/17 at 10:15am, Joerg Roedel wrote:
> > From: Joerg Roedel
> >
> > When booting into a kdump kernel, suppress IO_PAGE_FAULTs by
> > default for all devices. But allow the faults again when a
> > domain is assigned
On Fri, Jun 23, 2017 at 11:28:05AM +0530, Geetha sowjanya wrote:
[...]
> --- a/drivers/acpi/arm64/iort.c
> +++ b/drivers/acpi/arm64/iort.c
> @@ -828,6 +828,18 @@ static int __init arm_smmu_v3_count_resources(struct
> acpi_iort_node *node)
> return num_res;
> }
>
> +static bool arm_smmu_
On Fri Jun 23, 2017 at 11:35:25AM +0100, Robin Murphy wrote:
> On 23/06/17 09:56, Linu Cherian wrote:
> > On Fri Jun 23, 2017 at 11:23:26AM +0530, Linu Cherian wrote:
> >>
> >> Robin,
> >> Was trying to understand the new changes. Had few questions on
> >> arm_lpae_install_table.
> >>
> >> On Thu
On 23/06/17 09:56, Linu Cherian wrote:
> On Fri Jun 23, 2017 at 11:23:26AM +0530, Linu Cherian wrote:
>>
>> Robin,
>> Was trying to understand the new changes. Had few questions on
>> arm_lpae_install_table.
>>
>> On Thu Jun 22, 2017 at 04:53:54PM +0100, Robin Murphy wrote:
>>> For parallel I/O w
On Fri, Jun 23, 2017 at 06:59:33AM +0200, Robert Richter wrote:
> On 23.06.17 06:55:41, Robert Richter wrote:
> > On 22.06.17 22:04:37, Lorenzo Pieralisi wrote:
> > > On Thu, Jun 22, 2017 at 09:35:35PM +0200, Robert Richter wrote:
> > > > On 22.06.17 19:58:22, Will Deacon wrote:
> > > > > On Thu, J
On Fri, Jun 16, 2017 at 01:56:19PM -0500, Tom Lendacky wrote:
> Add the support to encrypt the kernel in-place. This is done by creating
> new page mappings for the kernel - a decrypted write-protected mapping
> and an encrypted mapping. The kernel is encrypted by copying it through
> a temporary b
On 23/06/17 09:47, John Garry wrote:
> On 22/06/2017 16:53, Robin Murphy wrote:
>> The feedback has been promising, so v2 is just a final update to cover
>> a handful of memory ordering and cosmetic tweaks that came up when Will
>> and I went through this offline.
>>
>> Thanks,
>> Robin.
>
> Hi Ro
On Fri, Jun 16, 2017 at 01:56:07PM -0500, Tom Lendacky wrote:
> When accessing memory using /dev/mem (or /dev/kmem) use the proper
> encryption attributes when mapping the memory.
>
> To insure the proper attributes are applied when reading or writing
> /dev/mem, update the xlate_dev_mem_ptr() fun
On Fri, Jun 16, 2017 at 01:55:54PM -0500, Tom Lendacky wrote:
> Xen does not currently support SME for PV guests. Clear the SME cpu
nitpick: s/cpu/CPU/
> capability in order to avoid any ambiguity.
>
> Signed-off-by: Tom Lendacky
> ---
> arch/x86/xen/enlighten_pv.c |1 +
> 1 file changed,
Hi dear Joerg,
On 06/16/17 at 10:15am, Joerg Roedel wrote:
> From: Joerg Roedel
>
> When booting into a kdump kernel, suppress IO_PAGE_FAULTs by
> default for all devices. But allow the faults again when a
> domain is assigned to a device.
I have two bugs at hand reported by customer, saying th
On Fri Jun 23, 2017 at 11:23:26AM +0530, Linu Cherian wrote:
>
> Robin,
> Was trying to understand the new changes. Had few questions on
> arm_lpae_install_table.
>
> On Thu Jun 22, 2017 at 04:53:54PM +0100, Robin Murphy wrote:
> > For parallel I/O with multiple concurrent threads servicing the
On Fri, Jun 16, 2017 at 01:55:45PM -0500, Tom Lendacky wrote:
> Provide support so that kexec can be used to boot a kernel when SME is
> enabled.
>
> Support is needed to allocate pages for kexec without encryption. This
> is needed in order to be able to reboot in the kernel in the same manner
>
On 22/06/2017 16:53, Robin Murphy wrote:
The feedback has been promising, so v2 is just a final update to cover
a handful of memory ordering and cosmetic tweaks that came up when Will
and I went through this offline.
Thanks,
Robin.
Hi Robin,
Is it worth us retesting this patchset?
If yes, as
On Fri, Jun 23, 2017 at 06:55:41AM +0200, Robert Richter wrote:
> On 22.06.17 22:04:37, Lorenzo Pieralisi wrote:
> > On Thu, Jun 22, 2017 at 09:35:35PM +0200, Robert Richter wrote:
> > > On 22.06.17 19:58:22, Will Deacon wrote:
> > > > On Thu, Jun 22, 2017 at 07:22:57PM +0100, Will Deacon wrote:
>
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