On Fri, Jun 9, 2017 at 3:07 AM, Robin Murphy wrote:
> On 08/06/17 15:35, Tomasz Figa wrote:
>> On Thu, Jun 8, 2017 at 10:22 PM, Robin Murphy wrote:
>>> On 07/06/17 10:47, Tomasz Figa wrote:
Hi Yong,
+Robin, Joerg, IOMMU ML
Please see my comments inline.
On Tue,
On Thu, Jun 8, 2017 at 2:28 PM, Lorenzo Pieralisi
wrote:
> On Tue, May 30, 2017 at 05:33:39PM +0530, Geetha sowjanya wrote:
>> From: Linu Cherian
>>
>> Cavium ThunderX2 implementation doesn't support second page in SMMU
>> register space. Hence, resource size is set as 64k for this model.
>>
>> S
On Fri, Jun 9, 2017 at 1:43 AM, Sakari Ailus wrote:
> Hi Tomasz,
>
> On Wed, Jun 07, 2017 at 05:35:13PM +0900, Tomasz Figa wrote:
>> Hi Yong, Tuukka,
>>
>> Continuing from yesterday. Please see comments inline.
>>
>> > On Tue, Jun 6, 2017 at 5:39 AM, Yong Zhi wrote:
>> [snip]
>> >> + ptr =
On 08/06/2017 22:17, Boris Ostrovsky wrote:
> On 06/08/2017 05:02 PM, Tom Lendacky wrote:
>> On 6/8/2017 3:51 PM, Boris Ostrovsky wrote:
> What may be needed is making sure X86_FEATURE_SME is not set for PV
> guests.
And that may be something that Xen will need to control through eithe
I will test as soon as I can, just getting ready for summer vacation right
now
On Jun 8, 2017 14:34, "Jan Vesely" wrote:
> On Tue, 2017-06-06 at 10:02 +, Nath, Arindam wrote:
> > > -Original Message-
> > > From: Lendacky, Thomas
> > > Sent: Tuesday, June 06, 2017 1:23 AM
> > > To: io
On 6/8/2017 2:58 AM, Christoph Hellwig wrote:
On Wed, Jun 07, 2017 at 02:17:32PM -0500, Tom Lendacky wrote:
Add warnings to let the user know when bounce buffers are being used for
DMA when SME is active. Since the bounce buffers are not in encrypted
memory, these notifications are to allow the
On 6/8/2017 1:05 AM, Andy Lutomirski wrote:
On Wed, Jun 7, 2017 at 12:14 PM, Tom Lendacky wrote:
The cr3 register entry can contain the SME encryption bit that indicates
the PGD is encrypted. The encryption bit should not be used when creating
a virtual address for the PGD table.
Create a new
On 06/08/2017 05:02 PM, Tom Lendacky wrote:
> On 6/8/2017 3:51 PM, Boris Ostrovsky wrote:
>>
>>>
What may be needed is making sure X86_FEATURE_SME is not set for PV
guests.
>>>
>>> And that may be something that Xen will need to control through either
>>> CPUID or MSR support for the PV g
://github.com/0day-ci/linux/commits/Tom-Lendacky/x86-Secure-Memory-Encryption-AMD/20170608-104147
config: sparc-defconfig (attached as .config)
compiler: sparc-linux-gcc (GCC) 6.2.0
reproduce:
wget
https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
On 6/8/2017 3:51 PM, Boris Ostrovsky wrote:
What may be needed is making sure X86_FEATURE_SME is not set for PV
guests.
And that may be something that Xen will need to control through either
CPUID or MSR support for the PV guests.
Only on newer versions of Xen. On earlier versions (2-3 y
>
>> What may be needed is making sure X86_FEATURE_SME is not set for PV
>> guests.
>
> And that may be something that Xen will need to control through either
> CPUID or MSR support for the PV guests.
Only on newer versions of Xen. On earlier versions (2-3 years old) leaf
0x8007 is passed to
On Tue, 2017-06-06 at 10:02 +, Nath, Arindam wrote:
> > -Original Message-
> > From: Lendacky, Thomas
> > Sent: Tuesday, June 06, 2017 1:23 AM
> > To: iommu@lists.linux-foundation.org
> > Cc: Nath, Arindam ; Joerg Roedel
> > ; Duran, Leo ; Suthikulpanit,
> > Suravee
> > Subject: [PATCH
From: Shaohua Li
I made a mistake in commit bfd20f1. We should skip the force on with the
option enabled instead of vice versa. Not sure why this passed our
performance test, sorry.
Fix: bfd20f1(x86, iommu/vt-d: Add an option to disable Intel IOMMU force on)
Signed-off-by: Shaohua Li
---
arch/
On 08/06/17 15:35, Tomasz Figa wrote:
> On Thu, Jun 8, 2017 at 10:22 PM, Robin Murphy wrote:
>> On 07/06/17 10:47, Tomasz Figa wrote:
>>> Hi Yong,
>>>
>>> +Robin, Joerg, IOMMU ML
>>>
>>> Please see my comments inline.
>>>
>>> On Tue, Jun 6, 2017 at 5:39 AM, Yong Zhi wrote:
> [snip]
+
+/
On 08/06/17 18:13, Rafael J. Wysocki wrote:
> On Thu, Jun 8, 2017 at 6:32 PM, Lorenzo Pieralisi
> wrote:
>> On Tue, May 30, 2017 at 05:33:38PM +0530, Geetha sowjanya wrote:
>>> Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas.
>>> 1. Errata ID #74
>>>SMMU register alias Page 1 is
On Thu, Jun 8, 2017 at 6:32 PM, Lorenzo Pieralisi
wrote:
> On Tue, May 30, 2017 at 05:33:38PM +0530, Geetha sowjanya wrote:
>> Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas.
>> 1. Errata ID #74
>>SMMU register alias Page 1 is not implemented
>> 2. Errata ID #126
>>SMMU doe
Hi Tomasz and Alan,
On Thu, Jun 08, 2017 at 11:55:18AM +0900, Tomasz Figa wrote:
> Hi Alan,
>
> On Thu, Jun 8, 2017 at 2:45 AM, Alan Cox wrote:
> >> > + struct ipu3_mmu *mmu = to_ipu3_mmu(dev);
> >> > + dma_addr_t daddr = iommu_iova_to_phys(mmu->domain, dma_handle);
> >> > +
> >> > +
Hi Tomasz,
On Wed, Jun 07, 2017 at 05:35:13PM +0900, Tomasz Figa wrote:
> Hi Yong, Tuukka,
>
> Continuing from yesterday. Please see comments inline.
>
> > On Tue, Jun 6, 2017 at 5:39 AM, Yong Zhi wrote:
> [snip]
> >> + ptr = ipu3_mmu_alloc_page_table(mmu_dom, false);
> >> + if (!pt
On 06/08/2017 06:25 AM, Christoph Hellwig wrote:
> DMA_ERROR_CODE is not a public API and will go away. Instead properly
> unwind based on the loop counter.
>
> Signed-off-by: Christoph Hellwig
Acked-by: Dave Jiang
> ---
> drivers/dma/ioat/init.c | 24 +++-
> 1 file chang
On Tue, May 30, 2017 at 05:33:38PM +0530, Geetha sowjanya wrote:
> Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas.
> 1. Errata ID #74
>SMMU register alias Page 1 is not implemented
> 2. Errata ID #126
>SMMU doesnt support unique IRQ lines and also MSI for gerror,
>eventq
On Thu, 8 Jun 2017 15:25:44 +0200
Christoph Hellwig wrote:
> s390 can also use noop_dma_ops, and while that currently does not return
> errors it will so in the future. Implementing the mapping_error method
> is the proper way to have per-ops error conditions.
>
> Signed-off-by: Christoph Hell
On 6/7/2017 9:40 PM, Nick Sarnie wrote:
On Wed, Jun 7, 2017 at 3:13 PM, Tom Lendacky wrote:
This patch series provides support for AMD's new Secure Memory Encryption (SME)
feature.
SME can be used to mark individual pages of memory as encrypted through the
page tables. A page of memory that is
BOn Thu, Jun 08, 2017 at 03:25:50PM +0200, Christoph Hellwig wrote:
> +static int dmabounce_mapping_error(struct device *dev, dma_addr_t dma_addr)
> +{
> + if (dev->archdata.dmabounce)
> + return 0;
I'm not convinced that we need this check here:
dev->archdata.dmabounce =
On Thu, Jun 8, 2017 at 10:22 PM, Robin Murphy wrote:
> On 07/06/17 10:47, Tomasz Figa wrote:
>> Hi Yong,
>>
>> +Robin, Joerg, IOMMU ML
>>
>> Please see my comments inline.
>>
>> On Tue, Jun 6, 2017 at 5:39 AM, Yong Zhi wrote:
[snip]
>>> +
>>> +/* End of things adapted from arch/arm/mm/dma-mapping
DMA_ERROR_CODE is going to go away, so don't rely on it.
Signed-off-by: Christoph Hellwig
---
arch/sparc/include/asm/dma-mapping.h | 2 --
arch/sparc/kernel/iommu.c| 12 +---
arch/sparc/kernel/iommu_common.h | 2 ++
arch/sparc/kernel/pci_sun4v.c| 14 ++--
On 6/7/2017 9:38 PM, Nick Sarnie wrote:
On Wed, Jun 7, 2017 at 3:17 PM, Tom Lendacky wrote:
The IOMMU is programmed with physical addresses for the various tables
and buffers that are used to communicate between the device and the
driver. When the driver allocates this memory it is encrypted. I
Same behavior, less code duplication.
Signed-off-by: Christoph Hellwig
---
arch/arm/common/dmabounce.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index 4aabf117e136..d89a0b56b245 100644
--- a/arch/arm/commo
By the time cell_pci_dma_dev_setup calls cell_dma_dev_setup no device can
have the fixed map_ops set yet as it's only set by the set_dma_mask
method. So move the setup for the fixed case to be only called in that
place instead of indirecting through cell_dma_dev_setup.
Signed-off-by: Christoph He
This implementation is simply bogus - hexagon only has a simple
direct mapped DMA implementation and thus doesn't care about the
address.
Signed-off-by: Christoph Hellwig
---
arch/hexagon/include/asm/dma-mapping.h | 2 --
arch/hexagon/kernel/dma.c | 9 -
2 files changed, 11
From: Christoph Hellwig
Date: Thu, 8 Jun 2017 15:25:45 +0200
> DMA_ERROR_CODE is going to go away, so don't rely on it.
>
> Signed-off-by: Christoph Hellwig
Acked-by: David S. Miller
___
iommu mailing list
iommu@lists.linux-foundation.org
https://l
Hi Christoph,
On Thu, Jun 8, 2017 at 11:25 PM, Christoph Hellwig wrote:
> Usually dma_supported decisions are done by the dma_map_ops instance.
> Switch sparc to that model by providing a ->dma_supported instance for
> sbus that always returns false, and implementations tailored to the sun4u
> an
From: Christoph Hellwig
Date: Thu, 8 Jun 2017 15:25:53 +0200
> Usually dma_supported decisions are done by the dma_map_ops instance.
> Switch sparc to that model by providing a ->dma_supported instance for
> sbus that always returns false, and implementations tailored to the sun4u
> and sun4v ca
From: Christoph Hellwig
Date: Thu, 8 Jun 2017 15:25:52 +0200
> We can just use pci32_dma_ops.
>
> Btw, given that leon is 32-bit and appears to be PCI based, do even need
> the special case for it in get_arch_dma_ops at all?
I would need to defer to the LEON developers on that, but they haven'
From: Christoph Hellwig
Date: Thu, 8 Jun 2017 15:25:27 +0200
> That way the driver doesn't have to rely on DMA_ERROR_CODE, which
> is not a public API and going away.
>
> Signed-off-by: Christoph Hellwig
Acked-by: David S. Miller
___
iommu mailing
From: Christoph Hellwig
Date: Thu, 8 Jun 2017 15:25:25 +0200
> for a while we have a generic implementation of the dma mapping routines
> that call into per-arch or per-device operations. But right now there
> still are various bits in the interfaces where don't clearly operate
> on these ops.
DMA_ERROR_CODE is going to go away, so don't rely on it.
Signed-off-by: Christoph Hellwig
---
arch/x86/kernel/pci-calgary_64.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
index f
Signed-off-by: Christoph Hellwig
---
arch/hexagon/include/asm/dma-mapping.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/hexagon/include/asm/dma-mapping.h
b/arch/hexagon/include/asm/dma-mapping.h
index 9c15cb5271a6..463dbc18f853 100644
--- a/arch/hexagon/include/asm/dma-mapping.h
+++
s390 can also use noop_dma_ops, and while that currently does not return
errors it will so in the future. Implementing the mapping_error method
is the proper way to have per-ops error conditions.
Signed-off-by: Christoph Hellwig
---
arch/s390/include/asm/dma-mapping.h | 2 --
arch/s390/pci/pci
These just duplicate the default behavior if no method is provided.
Signed-off-by: Christoph Hellwig
---
lib/dma-virt.c | 12
1 file changed, 12 deletions(-)
diff --git a/lib/dma-virt.c b/lib/dma-virt.c
index dcd4df1f7174..5c4f11329721 100644
--- a/lib/dma-virt.c
+++ b/lib/dma-virt
DMA_ERROR_CODE is going to go away, so don't rely on it. Instead
define a ->mapping_error method for all IOMMU based dma operation
instances. The direct ops don't ever return an error and don't
need a ->mapping_error method.
Signed-off-by: Christoph Hellwig
---
arch/powerpc/include/asm/dma-map
All dma_map_ops instances now handle their errors through
->mapping_error.
Signed-off-by: Christoph Hellwig
---
arch/x86/include/asm/dma-mapping.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/x86/include/asm/dma-mapping.h
b/arch/x86/include/asm/dma-mapping.h
index 08a0838b83fb..c35
This just duplicates the generic implementation.
Signed-off-by: Christoph Hellwig
---
drivers/xen/swiotlb-xen.c | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/xen/swiotlb-xen.c b/drivers/xen/swiotlb-xen.c
index c3a04b2d7532..82fc54f8eb77 100644
--- a/drivers/xen/swiotlb
Usually dma_supported decisions are done by the dma_map_ops instance.
Switch sparc to that model by providing a ->dma_supported instance for
sbus that always returns false, and implementations tailored to the sun4u
and sun4v cases for sparc64, and leave it unimplemented for PCI on
sparc32, which me
These just duplicate the default behavior if no method is provided.
Signed-off-by: Christoph Hellwig
---
lib/dma-noop.c | 12
1 file changed, 12 deletions(-)
diff --git a/lib/dma-noop.c b/lib/dma-noop.c
index de26c8b68f34..643a074f139d 100644
--- a/lib/dma-noop.c
+++ b/lib/dma-noop
Same behavior, less code duplication.
Signed-off-by: Christoph Hellwig
---
arch/mips/loongson64/common/dma-swiotlb.c | 19 +--
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git a/arch/mips/loongson64/common/dma-swiotlb.c
b/arch/mips/loongson64/common/dma-swiotlb.c
ind
And instead wire it up as method for all the dma_map_ops instances.
Note that this also means the arch specific check will be fully instead
of partially applied in the AMD iommu driver.
Signed-off-by: Christoph Hellwig
---
arch/x86/include/asm/dma-mapping.h | 3 ---
arch/x86/include/asm/iommu.h
DMA_ERROR_CODE is going to go away, so don't rely on it.
Signed-off-by: Christoph Hellwig
---
drivers/iommu/amd_iommu.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
index 63cacf5d6cf2..d41280e869de 1
On 08/06/17 14:25, Christoph Hellwig wrote:
> The dma alloc interface returns an error by return NULL, and the
> mapping interfaces rely on the mapping_error method, which the dummy
> ops already implement correctly.
>
> Thus remove the DMA_ERROR_CODE define.
Reviewed-by: Robin Murphy
> Signed-
Signed-off-by: Christoph Hellwig
---
arch/powerpc/kernel/dma.c | 4
include/linux/dma-mapping.h | 6 --
2 files changed, 10 deletions(-)
diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c
index 41c749586bd2..466c9f07b288 100644
--- a/arch/powerpc/kernel/dma.c
+++ b/arc
Hi Christoph,
On 08/06/17 14:25, Christoph Hellwig wrote:
> DMA_ERROR_CODE is not a public API and will go away soon. dma dma-iommu
> driver already implements a proper ->mapping_error method, so it's only
> using the value internally. Add a new local define using the value
> that arm64 which is
Signed-off-by: Christoph Hellwig
---
include/linux/dma-mapping.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index a57875309bfd..3e5908656226 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -549,7 +54
DMA_ERROR_CODE is going to go away, so don't rely on it.
Signed-off-by: Christoph Hellwig
---
arch/arm/common/dmabounce.c| 16 ---
arch/arm/include/asm/dma-iommu.h | 2 ++
arch/arm/include/asm/dma-mapping.h | 1 -
arch/arm/mm/dma-mapping.c | 41 ++
And instead wire it up as method for all the dma_map_ops instances.
Note that the code seems a little fishy for dmabounce and iommu, but
for now I'd like to preserve the existing behavior 1:1.
Signed-off-by: Christoph Hellwig
---
arch/arm/common/dmabounce.c| 1 +
arch/arm/include/asm/dm
Signed-off-by: Christoph Hellwig
---
arch/powerpc/include/asm/dma-mapping.h | 1 -
arch/powerpc/kernel/dma.c | 13 -
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/dma-mapping.h
b/arch/powerpc/include/asm/dma-mapping.h
index 73a
We can just use pci32_dma_ops.
Btw, given that leon is 32-bit and appears to be PCI based, do even need
the special case for it in get_arch_dma_ops at all?
Signed-off-by: Christoph Hellwig
---
arch/sparc/include/asm/dma-mapping.h | 3 +--
arch/sparc/kernel/ioport.c | 5 +
2 files
These just duplicate the default behavior if no method is provided.
Signed-off-by: Christoph Hellwig
---
arch/tile/kernel/pci-dma.c | 30 --
1 file changed, 30 deletions(-)
diff --git a/arch/tile/kernel/pci-dma.c b/arch/tile/kernel/pci-dma.c
index 569bb6dd154a..f2abe
And update the documentation - dma_mapping_error has been supported
everywhere for a long time.
Signed-off-by: Christoph Hellwig
---
Documentation/DMA-API-HOWTO.txt | 31 +--
include/linux/dma-mapping.h | 5 -
2 files changed, 5 insertions(+), 31 deletions(-)
Besides removing the last instance of the set_dma_mask method this also
reduced the code duplication.
Signed-off-by: Christoph Hellwig
---
arch/powerpc/platforms/cell/iommu.c | 25 +
1 file changed, 9 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/platforms/cel
This implementation is simply bogus - hexagon only has a simple
direct mapped DMA implementation and thus doesn't care about the
address.
Signed-off-by: Christoph Hellwig
---
arch/openrisc/include/asm/dma-mapping.h | 7 ---
1 file changed, 7 deletions(-)
diff --git a/arch/openrisc/include/a
DMA_ERROR_CODE is going to go away, so don't rely on it.
Signed-off-by: Christoph Hellwig
---
arch/x86/kernel/pci-nommu.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/pci-nommu.c b/arch/x86/kernel/pci-nommu.c
index a88952ef371c..085fe6ce4049 10064
On 6/7/2017 5:06 PM, Boris Ostrovsky wrote:
On 06/07/2017 03:14 PM, Tom Lendacky wrote:
The cr3 register entry can contain the SME encryption bit that indicates
the PGD is encrypted. The encryption bit should not be used when creating
a virtual address for the PGD table.
Create a new function,
The dma alloc interface returns an error by return NULL, and the
mapping interfaces rely on the mapping_error method, which the dummy
ops already implement correctly.
Thus remove the DMA_ERROR_CODE define.
Signed-off-by: Christoph Hellwig
---
arch/arm64/include/asm/dma-mapping.h | 1 -
arch/arm
Signed-off-by: Christoph Hellwig
---
arch/hexagon/include/asm/dma-mapping.h | 2 --
arch/hexagon/kernel/dma.c | 12 +---
arch/hexagon/kernel/hexagon_ksyms.c| 1 -
3 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/hexagon/include/asm/dma-mapping.h
b/ar
xtensa already implements the mapping_error method for its only
dma_map_ops instance.
Signed-off-by: Christoph Hellwig
---
arch/xtensa/include/asm/dma-mapping.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/xtensa/include/asm/dma-mapping.h
b/arch/xtensa/include/asm/dma-mapping.h
ind
sh does not return errors for dma_map_page.
Signed-off-by: Christoph Hellwig
---
arch/sh/include/asm/dma-mapping.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/sh/include/asm/dma-mapping.h
b/arch/sh/include/asm/dma-mapping.h
index d99008af5f73..9b06be07db4d 100644
--- a/arch/sh/inc
dma-noop is the only dma_mapping_ops instance for m32r and does not return
errors.
Signed-off-by: Christoph Hellwig
---
arch/m32r/include/asm/dma-mapping.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/m32r/include/asm/dma-mapping.h
b/arch/m32r/include/asm/dma-mapping.h
index c01d9f
microblaze does not return errors for dma_map_page.
Signed-off-by: Christoph Hellwig
---
arch/microblaze/include/asm/dma-mapping.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/microblaze/include/asm/dma-mapping.h
b/arch/microblaze/include/asm/dma-mapping.h
index 3fad5e722a66..e15cd
Signed-off-by: Christoph Hellwig
---
arch/c6x/include/asm/dma-mapping.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/arch/c6x/include/asm/dma-mapping.h
b/arch/c6x/include/asm/dma-mapping.h
index aca9f755e4f8..05daf1038111 100644
--- a/arch/c6x/include/asm/dma-mapping.h
+++ b/arch/c6x/
All ia64 dma_mapping_ops instances already have a mapping_error member.
Signed-off-by: Christoph Hellwig
---
arch/ia64/include/asm/dma-mapping.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/ia64/include/asm/dma-mapping.h
b/arch/ia64/include/asm/dma-mapping.h
index 73ec3c6f4cfe..3ce
openrisc does not return errors for dma_map_page.
Signed-off-by: Christoph Hellwig
---
arch/openrisc/include/asm/dma-mapping.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/openrisc/include/asm/dma-mapping.h
b/arch/openrisc/include/asm/dma-mapping.h
index 0c0075f17145..a4ea139c2ef9
DMA_ERROR_CODE is going to go away, so don't rely on it.
Signed-off-by: Christoph Hellwig
---
drivers/xen/swiotlb-xen.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/xen/swiotlb-xen.c b/drivers/xen/swiotlb-xen.c
index a0f006daab48..c3a04b2d7532 100644
DMA_ERROR_CODE is not a public API and will go away soon. dma dma-iommu
driver already implements a proper ->mapping_error method, so it's only
using the value internally. Add a new local define using the value
that arm64 which is the only current user of dma-iommu.
Signed-off-by: Christoph Hell
ARM and x86 had duplicated versions of the dma_ops structure, the
only difference is that x86 hasn't wired up the set_dma_mask,
mmap, and get_sgtable ops yet. On x86 all of them are identical
to the generic version, so they aren't needed but harmless.
All the symbols used only for xen_swiotlb_dma
DMA_ERROR_CODE already isn't a valid API to user for drivers and will
go away soon. exynos_drm_fb_dma_addr uses it a an error return when
the passed in index is invalid, but the callers never check for it
but instead pass the address straight to the hardware.
Add a WARN_ON instead and just return
dev_addr isn't even a dma_addr_t, and DMA_ERROR_CODE has never been
a valid driver API. Add a bool mapped flag instead.
Signed-off-by: Christoph Hellwig
---
drivers/gpu/drm/armada/armada_fb.c | 2 +-
drivers/gpu/drm/armada/armada_gem.c | 5 ++---
drivers/gpu/drm/armada/armada_gem.h | 1 +
3 fi
DMA_ERROR_CODE is not a public API and will go away. Instead properly
unwind based on the loop counter.
Signed-off-by: Christoph Hellwig
---
drivers/dma/ioat/init.c | 24 +++-
1 file changed, 7 insertions(+), 17 deletions(-)
diff --git a/drivers/dma/ioat/init.c b/drivers/dm
DMA_ERROR_CODE is not supposed to be used by drivers.
Signed-off-by: Christoph Hellwig
---
drivers/firmware/tegra/ivc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/firmware/tegra/ivc.c b/drivers/firmware/tegra/ivc.c
index 29ecfd815320..a01461d63f68 100644
---
That way the driver doesn't have to rely on DMA_ERROR_CODE, which
is not a public API and going away.
Signed-off-by: Christoph Hellwig
---
drivers/net/ethernet/ibm/ibmveth.c | 159 +
1 file changed, 74 insertions(+), 85 deletions(-)
diff --git a/drivers/net/e
Hi all,
for a while we have a generic implementation of the dma mapping routines
that call into per-arch or per-device operations. But right now there
still are various bits in the interfaces where don't clearly operate
on these ops. This series tries to clean up a lot of those (but not all
yet,
On 07/06/17 10:47, Tomasz Figa wrote:
> Hi Yong,
>
> +Robin, Joerg, IOMMU ML
>
> Please see my comments inline.
>
> On Tue, Jun 6, 2017 at 5:39 AM, Yong Zhi wrote:
>> IPU3 mmu based DMA mapping driver
>>
>> Signed-off-by: Yong Zhi
>> ---
>> drivers/media/pci/intel/ipu3/Kconfig | 6 +
>
On Mon, Jun 05, 2017 at 02:52:03PM -0500, Tom Lendacky wrote:
> This patch series addresses some performance issues in the AMD IOMMU
> driver:
>
> - Reduce the amount of MMIO performed during command submission
> - When the command queue is (near) full, only wait till there is enough
> room for
For parallel I/O with multiple concurrent threads servicing the same
device (or devices, if several share a domain), serialising page table
updates becomes a massive bottleneck. On reflection, though, we don't
strictly need to do that - for valid IOMMU API usage, there are in fact
only two races th
With the io-pgtable code now robust against (valid) races, we no longer
need to serialise all operations with a lock. This might make broken
callers who issue concurrent operations on overlapping addresses go even
more wrong than before, but hey, they already had little hope of useful
or determinis
Mirroring the LPAE implementation, rework the v7s code to be robust
against concurrent operations. The same two potential races exist, and
are solved in the same manner, with the fixed 2-level structure making
life ever so slightly simpler.
What complicates matters compared to LPAE, however, is la
Once we remove the serialising spinlock, a potential race opens up for
non-coherent IOMMUs whereby a caller of .map() can be sure that cache
maintenance has been performed on their new PTE, but will have no
guarantee that such maintenance for table entries above it has actually
completed (e.g. if a
As for SMMUv2, take advantage of io-pgtable's newfound tolerance for
concurrency. Unfortunately in this case the command queue lock remains a
point of serialisation for the unmap path, but there may be a little
more we can do to ameliorate that in future.
Signed-off-by: Robin Murphy
---
drivers/
Whilst we don't support the PXN bit at all, so should never encounter a
level 1 section or supersection PTE with it set, it would still be wise
to check both table type bits to resolve any theoretical ambiguity.
Signed-off-by: Robin Murphy
---
drivers/iommu/io-pgtable-arm-v7s.c | 3 ++-
1 file c
Hi all,
Here's the cleaned up nominally-final version of the patches everybody's
keen to see. #1 is just a non-critical thing-I-spotted-in-passing fix,
#2-#4 do some preparatory work (and bid farewell to everyone's least
favourite bit of code, hooray!), and #5-#8 do the dirty deed itself.
The bra
The current split_blk_unmap implementation suffers from some inscrutable
pointer trickery for creating the tables to replace the block entry, but
more than that it also suffers from hideous inefficiency. For example,
the most pathological case of unmapping a level 3 page from a level 1
block will a
Whilst the short-descriptor format's split_blk_unmap implementation has
no need to be recursive, it followed the pattern of the LPAE version
anyway for the sake of consistency. With the latter now reworked for
both efficiency and future scalability improvements, tweak the former
similarly, not leas
> -Original Message-
> From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com]
> Sent: Thursday, June 08, 2017 11:15 AM
> To: Shameerali Kolothum Thodi
> Cc: marc.zyng...@arm.com; sudeep.ho...@arm.com; will.dea...@arm.com;
> robin.mur...@arm.com; hanjun@linaro.org; Gabriele Paoloni
On Thu, Jun 08, 2017 at 09:09:28AM +, Shameerali Kolothum Thodi wrote:
>
>
> > -Original Message-
> > From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com]
> > Sent: Thursday, June 08, 2017 9:49 AM
> > To: Shameerali Kolothum Thodi
> > Cc: marc.zyng...@arm.com; sudeep.ho...@arm.c
> -Original Message-
> From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com]
> Sent: Wednesday, June 07, 2017 6:16 PM
> To: Shameerali Kolothum Thodi
> Cc: marc.zyng...@arm.com; sudeep.ho...@arm.com; will.dea...@arm.com;
> robin.mur...@arm.com; hanjun@linaro.org; Gabriele Paoloni
> -Original Message-
> From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com]
> Sent: Thursday, June 08, 2017 9:49 AM
> To: Shameerali Kolothum Thodi
> Cc: marc.zyng...@arm.com; sudeep.ho...@arm.com; will.dea...@arm.com;
> robin.mur...@arm.com; hanjun@linaro.org; Gabriele Paoloni;
On 08/06/2017 05:44, Ganapatrao Kulkarni wrote:
ARM IORT specification(rev. C) has added provision to define proximity
domain in SMMUv3 IORT table. Adding required code to parse Proximity
domain and set numa_node of smmv3 platform devices.
v3:
- Addressed Lorenzo Pieralisi comment.
v2:
- C
On Tue, May 30, 2017 at 05:33:39PM +0530, Geetha sowjanya wrote:
> From: Linu Cherian
>
> Cavium ThunderX2 implementation doesn't support second page in SMMU
> register space. Hence, resource size is set as 64k for this model.
>
> Signed-off-by: Linu Cherian
> Signed-off-by: Geetha Sowjanya
>
On Tue, Jun 06, 2017 at 03:01:36PM +, Shameerali Kolothum Thodi wrote:
[...]
> > > + irq_dom = pci_msi_get_device_domain(to_pci_dev(dev));
> > > + if (irq_dom) {
> > > + int ret;
> > > + u32 rid;
> > > +
> > > + rid = pci_msi_domain_get_msi_rid(irq_dom,
> > to_
On Wed, Jun 07, 2017 at 02:17:32PM -0500, Tom Lendacky wrote:
> Add warnings to let the user know when bounce buffers are being used for
> DMA when SME is active. Since the bounce buffers are not in encrypted
> memory, these notifications are to allow the user to determine some
> appropriate actio
On Wed, Jun 7, 2017 at 12:14 PM, Tom Lendacky wrote:
> The cr3 register entry can contain the SME encryption bit that indicates
> the PGD is encrypted. The encryption bit should not be used when creating
> a virtual address for the PGD table.
>
> Create a new function, read_cr3_pa(), that will ex
-Secure-Memory-Encryption-AMD/20170608-104147
config: um-x86_64_defconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
# save the attached .config to linux build tree
make ARCH=um SUBARCH=x86_64
All errors (new ones prefixed by >>):
I
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