On Wed, Apr 5, 2017 at 9:01 AM, Nath, Arindam wrote:
>
> >-Original Message-
> >From: Daniel Drake [mailto:dr...@endlessm.com]
> >Sent: Thursday, March 30, 2017 7:15 PM
> >To: Nath, Arindam
> >Cc: j...@8bytes.org; Deucher, Alexander; Bridgman, John; amd-
> >g...@lists.freedesktop.org; iomm
On Thu, May 04, 2017 at 09:34:33AM -0400, Rob Clark wrote:
> Cc: devicet...@vger.kernel.org
> Signed-off-by: Rob Clark
> ---
> .../devicetree/bindings/iommu/qcom,iommu.txt | 121
> +
> 1 file changed, 121 insertions(+)
> create mode 100644 Documentation/devicetree/bind
On Sat May 06, 2017 at 12:22:50AM +0200, Robert Richter wrote:
> On 05.05.17 17:38:04, Geetha sowjanya wrote:
> > From: Linu Cherian
> >
> > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas.
> > 1. Errata ID #74
> >SMMU register alias Page 1 is not implemented
> > 2. Errata ID #
Hi,
On 5/8/2017 4:53 PM, Marek Szyprowski wrote:
> Hi Sricharan,
>
> On 2017-04-10 13:20, Sricharan R wrote:
>> This series calls the dma ops configuration for the devices
>> at a generic place so that it works for all busses.
>> The dma_configure_ops for a device is now called during
>> the devi
On 5/7/2017 12:18 PM, Borislav Petkov wrote:
On Tue, Apr 18, 2017 at 04:19:00PM -0500, Tom Lendacky wrote:
The efi_mem_type() function currently returns a 0, which maps to
EFI_RESERVED_TYPE, if the function is unable to find a memmap entry for
the supplied physical address. Returning EFI_RESERVE
On 08.05.17 16:20:49, Linu Cherian wrote:
>
> On Mon May 08, 2017 at 12:09:32PM +0200, Robert Richter wrote:
> > On 08.05.17 15:14:37, Linu Cherian wrote:
> > > On Sat May 06, 2017 at 12:18:44AM +0200, Robert Richter wrote:
> > > > On 05.05.17 17:38:06, Geetha sowjanya wrote:
> > > > > From: Linu
On Mon, May 8, 2017 at 4:51 PM, Robin Murphy wrote:
> On 05/05/17 13:08, Geetha sowjanya wrote:
>> From: Geetha Sowjanya
>>
>> Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq
>> lines for gerror, eventq and cmdq-sync.
>>
>> This patch addresses the issue by checking if
Hi Sricharan,
On 2017-04-10 13:20, Sricharan R wrote:
This series calls the dma ops configuration for the devices
at a generic place so that it works for all busses.
The dma_configure_ops for a device is now called during
the device_attach callback just before the probe of the
bus/driver is call
On 05/05/17 13:08, Geetha sowjanya wrote:
> From: Geetha Sowjanya
>
> Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq
> lines for gerror, eventq and cmdq-sync.
>
> This patch addresses the issue by checking if any interrupt sources are
> using same irq number, then the
On Mon, May 08, 2017 at 10:38:09AM +, Liu, Yi L wrote:
> On Thu, 27 Apr 2017 18:53:17 +0800
> Peter Xu wrote:
>
> > On Wed, Apr 26, 2017 at 06:06:33PM +0800, Liu, Yi L wrote:
> > > Expose "Shared Virtual Memory" to guest by using "svm" option.
> > > Also use "svm" to expose SVM related capabi
On Mon, May 8, 2017 at 3:39 PM, Robert Richter
wrote:
> On 08.05.17 15:14:37, Linu Cherian wrote:
>> On Sat May 06, 2017 at 12:18:44AM +0200, Robert Richter wrote:
>> > On 05.05.17 17:38:06, Geetha sowjanya wrote:
>> > > From: Linu Cherian
>> > >
>> > > With implementations supporting only page 0
On Mon May 08, 2017 at 12:09:32PM +0200, Robert Richter wrote:
> On 08.05.17 15:14:37, Linu Cherian wrote:
> > On Sat May 06, 2017 at 12:18:44AM +0200, Robert Richter wrote:
> > > On 05.05.17 17:38:06, Geetha sowjanya wrote:
> > > > From: Linu Cherian
> > > >
> > > > With implementations support
On Thu, 27 Apr 2017 18:53:17 +0800
Peter Xu wrote:
> On Wed, Apr 26, 2017 at 06:06:33PM +0800, Liu, Yi L wrote:
> > Expose "Shared Virtual Memory" to guest by using "svm" option.
> > Also use "svm" to expose SVM related capabilities to guest.
> > e.g. "-device intel-iommu, svm=on"
> >
> > Signed-
On 08.05.17 15:14:37, Linu Cherian wrote:
> On Sat May 06, 2017 at 12:18:44AM +0200, Robert Richter wrote:
> > On 05.05.17 17:38:06, Geetha sowjanya wrote:
> > > From: Linu Cherian
> > >
> > > With implementations supporting only page 0 register space,
> > > resource size can be 64k as well and h
On 08.05.17 10:59:46, Robin Murphy wrote:
> On 08/05/17 10:17, Linu Cherian wrote:
> > This actually results in more lines of changes. If you think the below
> > approach is still better, will post a V4 of this series with this change.
>
> Why not just do this?:
>
> static inline unsigned long pa
On 08/05/17 10:17, Linu Cherian wrote:
> On Sat May 06, 2017 at 01:03:28AM +0200, Robert Richter wrote:
>> On 05.05.17 17:38:05, Geetha sowjanya wrote:
>>> From: Linu Cherian
>>>
>>> Cavium ThunderX2 SMMU implementation doesn't support page 1 register space
>>> and PAGE0_REGS_ONLY option will be e
On Sat May 06, 2017 at 12:18:44AM +0200, Robert Richter wrote:
> On 05.05.17 17:38:06, Geetha sowjanya wrote:
> > From: Linu Cherian
> >
> > With implementations supporting only page 0 register space,
> > resource size can be 64k as well and hence perform size checks
> > based on SMMU option PAGE
On 07/05/17 01:06, Jon Masters wrote:
> On 05/09/2016 06:00 AM, Robin Murphy wrote:
>> On 09/05/16 10:37, Robin Murphy wrote:
>>> Hi Niklas,
>>>
>>> On 08/05/16 11:59, Niklas Söderlund wrote:
Hi,
While using CONFIG_DMA_API_DEBUG i came across this warning which I
think is a fals
On 08.05.17 14:47:39, Linu Cherian wrote:
> Have pasted here the relevant changes for doing fixups on smmu base instead
> of offset to get feedback.
To me this looks better than the ARM_SMMU_EVTQ_*() macros. It still
needs some more shaping (e.g. maybe remove page1_base var and call
arm_smmu_page
On Sat May 06, 2017 at 01:03:28AM +0200, Robert Richter wrote:
> On 05.05.17 17:38:05, Geetha sowjanya wrote:
> > From: Linu Cherian
> >
> > Cavium ThunderX2 SMMU implementation doesn't support page 1 register space
> > and PAGE0_REGS_ONLY option will be enabled as an errata workaround.
> >
> >
Hi Jon,
On Sun, May 7, 2017 at 2:06 AM, Jon Masters wrote:
> On 05/09/2016 06:00 AM, Robin Murphy wrote:
>> On 09/05/16 10:37, Robin Murphy wrote:
>>> On 08/05/16 11:59, Niklas Söderlund wrote:
While using CONFIG_DMA_API_DEBUG i came across this warning which I
think is a false positive
On Mon, May 08, 2017 at 12:09:42PM +0800, Xiao Guangrong wrote:
>
> Hi Liu Yi,
>
> I haven't started to read the code yet, however, could you
> detail more please? It emulates a SVM capable iommu device in
> a VM? Or It speeds up device's DMA access in a VM? Or it is a
> new facility introduced f
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