The iopgtable_store_entry_core() function uses a BUG() statement
for an unsupported page size entry programming. Replace this with
a less severe WARN_ON() and perform a graceful bailout on error.
Signed-off-by: Suman Anna
---
drivers/iommu/omap-iommu.c | 4 +++-
1 file changed, 3 insertions(+),
The OMAP IOMMU page table needs to be aligned on a 16K boundary,
and the current code uses a BUG_ON on the alignment sanity check
in the .domain_alloc() ops implementation. Replace this with a
less severe WARN_ON and bail out gracefully.
Signed-off-by: Suman Anna
---
drivers/iommu/omap-iommu.c |
This patch fixes one existing alignment checkpatch check
warning of the type "Alignment should match open parenthesis"
in the OMAP IOMMU debug source file.
Signed-off-by: Suman Anna
---
drivers/iommu/omap-iommu-debug.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i
The function iopgtable_clear_entry_all() is used for clearing all
the page table entries. These entries are neither created nor
initialized during the OMAP IOMMU driver probe, and are managed
only when a client device attaches to the IOMMU. So, there is no
need to invoke this function on a driver r
Hi Joerg,
Following are some minor cleanups to the OMAP IOMMU driver intended
for the next merge window.
Patch 1 fixes a crash when the IOMMU device is attempted to be unbound
from the driver using sysfs when no clients were attached to the MMU.
This is not a critical failure during normal usage
From: Borislav Petkov
Signed-off-by: Borislav Petkov
Cc: oprofile-l...@lists.sf.net
Cc: iommu@lists.linux-foundation.org
Cc: linux...@vger.kernel.org
---
arch/x86/events/core.c | 2 +-
arch/x86/include/asm/cpufeature.h| 1 -
arch/x86/include/asm/irq_work.h |
Joerg Roedel writes:
>
> Hi Tobias,
>
> On Thu, Dec 10, 2015 at 12:07:57AM +0100, Tobias Geiger wrote:
> > It all comes down to kernel > 4.1 && iommu=on = not working here
> >
> > Hardware is:
> > Intel DX58SO, Intel CPU i7 920... all pretty solid running for years
now,
> > always with iommo
Hi,
On 03/31/2016 05:59 PM, Boris Brezillon wrote:
> Add an helper to check if a virtual address is in the highmem region.
>
> Signed-off-by: Boris Brezillon
> ---
> include/linux/highmem.h | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/include/linux/highmem.h b/includ
From: Joerg Roedel
With this macro any user can easily iterate over a list of
phandles. The patch also converts __of_parse_phandle_with_args()
to make use of the macro.
The of_count_phandle_with_args() function is not converted,
because the macro hides the return value of of_phandle_iterator_ini
From: Joerg Roedel
Remove the usage of of_parse_phandle_with_args() and replace
it by the phandle-iterator implementation so that we can
parse out all of the potentially present 128 stream-ids.
Signed-off-by: Joerg Roedel
---
drivers/iommu/arm-smmu.c | 38 ++
From: Joerg Roedel
This struct carrys all necessary information to iterate over
a list of phandles and extract the arguments. Add an
init-function for the iterator and make use of it in
__of_parse_phandle_with_args().
Signed-off-by: Joerg Roedel
Acked-by: Rob Herring
---
drivers/of/base.c |
From: Joerg Roedel
The index = -1 case in __of_parse_phandle_with_args() is
used to just return the number of phandles. That special
case needs extra handling, so move it to the place where it
is needed: of_count_phandle_with_args().
This allows to further simplify __of_parse_phandle_with_args()
From: Joerg Roedel
Move the code to walk over the phandles out of the loop in
__of_parse_phandle_with_args() to a separate function that
just works with the iterator handle: of_phandle_iterator_next().
Signed-off-by: Joerg Roedel
Acked-by: Rob Herring
---
drivers/of/base.c | 130
From: Joerg Roedel
This helper function can be used to copy the arguments of a
phandle to an array.
Signed-off-by: Joerg Roedel
Acked-by: Rob Herring
---
drivers/of/base.c | 29 +++--
include/linux/of.h | 10 ++
2 files changed, 33 insertions(+), 6 deletions(-
Hi,
here is a new version of the implementation of the iterator
over phandles concept which Rob Herring suggested to me some
time ago. My approach is a little bit different from what
the diff showed back then, but it gets rid of the allocation
and 'struct of_phandle_args' misuse.
I also converted
On Wed, Mar 23, 2016 at 03:37:44PM -0500, Rob Herring wrote:
> On Wed, Mar 23, 2016 at 6:54 AM, Joerg Roedel wrote:
> > Thanks a lot for your fast reply! I guess these patches will go through
> > the DT tree, or should I carry them in the IOMMU tree? The DT tree
> > probably makes more sense.
>
>
On Mon, 4 Apr 2016 13:44:11 +0530
Vignesh R wrote:
> Hi,
>
> On 03/31/2016 05:59 PM, Boris Brezillon wrote:
> > Add an helper to check if a virtual address is in the highmem region.
> >
> > Signed-off-by: Boris Brezillon
> > ---
> > include/linux/highmem.h | 13 +
> > 1 file chang
On Wed, Mar 23, 2016 at 11:18:25PM +0800, kbuild test robot wrote:
>drivers/iommu/arm-smmu.c: In function 'arm_smmu_device_dt_probe':
>drivers/iommu/arm-smmu.c:1746:29: error: storage size of 'it' isn't known
> struct of_phandle_iterator it;
> ^
> >> dri
Hi Will,
On Tue, Mar 29, 2016 at 06:22:16PM +0100, Will Deacon wrote:
> > +
> > + if (i == 0)
> > + goto out_put_masters;
>
> I'm confused by this hunk. If i == 0, then we shouldn't have registered
> any masters and therefore out_put_masters won't have anything to do.
The idea was th
Hi Clemens,
On Sun, Apr 03, 2016 at 08:59:53AM +0200, Clemens Ladisch wrote:
> there are several reports of Xonar PCIe sound cards failing to work in
> kernel 4.4 (including 4.4.5):
>
> https://bugzilla.redhat.com/show_bug.cgi?id=1313790
> https://bugzilla.kernel.org/show_bug.cgi?id=111711
> http
Hi Will,
On 04/01/2016 06:19 PM, Will Deacon wrote:
> Commit cbf8277ef456 ("iommu/arm-smmu: Treat IOMMU_DOMAIN_DMA as bypass
> for now") ignores requests to attach a device to the default domain
> since, without IOMMU-basked DMA ops available everywhere, the default
> domain will just lead to unexp
On 04/04/2016 11:30 AM, kbuild test robot wrote:
> Hi Eric,
>
> [auto build test ERROR on iommu/next]
> [also build test ERROR on v4.6-rc2 next-20160404]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improving the system]
>
> url:
Hi Eric,
[auto build test ERROR on iommu/next]
[also build test ERROR on v4.6-rc2 next-20160404]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Eric-Auger/KVM-PCIe-MSI-passthrough-on-ARM
On 04/04/2016 11:22 AM, kbuild test robot wrote:
> Hi Eric,
>
> [auto build test ERROR on tip/irq/core]
> [also build test ERROR on v4.6-rc2 next-20160404]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improving the system]
>
> url:
Hi Eric,
[auto build test ERROR on tip/irq/core]
[also build test ERROR on v4.6-rc2 next-20160404]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Eric-Auger/KVM-PCIe-MSI-passthrough-on-ARM
On x86 IRQ remapping is abstracted by the IOMMU. On ARM this is abstracted
by the msi controller. vfio_safe_irq_domain allows to check whether
interrupts are "safe" for a given device. They are if the device does
not use MSI or if the device uses MSI and the msi-parent controller
supports IRQ remap
This series allows the user-space to register a reserved IOVA domain.
This completes the kernel integration of the whole functionality on top
of part 1 & 2.
We reuse the VFIO DMA MAP ioctl with a new flag to bridge to the
dma-reserved-iommu API. The number of IOVA pages to provision for MSI
bindin
The user is allowed to [un]register a reserved IOVA range by using the
DMA MAP API and setting the new flag: VFIO_DMA_MAP_FLAG_MSI_RESERVED_IOVA.
It provides the base address and the size. This region is stored in the
vfio_dma rb tree. At that point the iova range is not mapped to any target
addres
Do not advertise IOMMU_CAP_INTR_REMAP for arm-smmu. Indeed the
irq_remapping capability is abstracted on irqchip side for ARM as
opposed to Intel IOMMU featuring IRQ remapping HW.
So to check IRQ remapping capability, the msi domain needs to be
checked instead.
This commit needs to be applied aft
This patch allows the user-space to know whether MSI addresses need to
be mapped in the IOMMU. The user-space uses VFIO_IOMMU_GET_INFO ioctl and
IOMMU_INFO_REQUIRE_MSI_MAP gets set if they need to.
Also the number of IOMMU pages requested to map those is returned in
msi_iova_pages field. User-spac
We introduce a vfio_dma type since we will need to discriminate
legacy vfio_dma's from new reserved ones. Since those latter are
not mapped at registration, some treatments need to be reworked:
removal, replay. Currently they are unplugged. In subsequent patches
they will be reworked.
Signed-off-b
We plan to use msi_get_domain_info in VFIO module so let's export it.
Signed-off-by: Eric Auger
---
v2 -> v3:
- remove static implementation in case CONFIG_PCI_MSI_IRQ_DOMAIN is not set
---
kernel/irq/msi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c
In case the msi is emitted by a device attached to an iommu domain
and this iommu domain requires MSI mapping, the msi address (aka
doorbell) must be mapped in the IOMMU. Else MSI write transaction
will cause a fault.
We handle the iommu mapping/unmapping anytime the msi address is
updated.
In ca
This series implements the MSI address mapping/unmapping in the MSI
sub-system. binding happens on msi_domain_set_affinity, msi_domain_activate,
msi_domain_deactivate.
a new MSI domain info flag value is introduced to report whether the msi domain
implements IRQ remapping. GIC v3 ITS is the first
The ITS is the first ARM MSI controller advertising the new
MSI_FLAG_IRQ_REMAPPING flag. It does so because it supports
interrupt translation service. This HW support offers isolation
of MSIs, feature used when using KVM device passthrough.
Signed-off-by: Eric Auger
---
v5: new
---
drivers/irq
Let's introduce a new msi_domain_info flag value, MSI_FLAG_IRQ_REMAPPING
meant to tell the domain supports IRQ REMAPPING, also known as Interrupt
Translation Service. On Intel HW this IRQ remapping capability is
abstracted on IOMMU side while on ARM it is abstracted on MSI controller
side. This fla
Introduce a new function whose role is to unmap all allocated
reserved IOVAs and free the reserved iova domain
Signed-off-by: Eric Auger
---
v5 -> v6:
- use spin_lock instead of mutex
v3 -> v4:
- previously "iommu/arm-smmu: relinquish reserved resources on
domain deletion"
---
drivers/iommu/
we will need to track which host physical addresses are mapped to
reserved IOVA. In that prospect we introduce a new RB tree indexed
by physical address. This RB tree only is used for reserved IOVA
bindings.
It is expected this RB tree will contain very few bindings. Those
generally correspond to
Introduce a new DOMAIN_ATTR_MSI_MAPPING domain attribute. If supported,
this means the MSI addresses need to be mapped in the IOMMU.
x86 IOMMUs typically don't expose the attribute since on x86, MSI write
transaction addresses always are within the 1MB PA region [FEE0_h -
FEF0_000h] window whi
This patch introduces iommu_get/put_single_reserved.
iommu_get_single_reserved allows to allocate a new reserved iova page
and map it onto the physical page that contains a given physical address.
Page size is the IOMMU page one. It is the responsability of the
system integrator to make sure the i
Introduce alloc/free_reserved_iova_domain in the IOMMU API.
alloc_reserved_iova_domain initializes an iova domain at a given
iova base address and with a given size. This iova domain will
be used to allocate iova within that window. Those IOVAs will be reserved
for special purpose, typically MSI fr
This series introduces the dma-reserved-iommu api used to:
- create/destroy an iova domain dedicated to reserved iova bindings
- map/unmap physical addresses onto reserved IOVAs.
- unmap and destroy all IOVA reserved bindings
Currently reserved IOVAs are meant to map MSI physical doorbells. A sing
This patch introduces some new fields in the iommu_domain struct,
dedicated to reserved iova management.
In a similar way as DMA mapping IOVA window, we need to store
information related to a reserved IOVA window.
The reserved_iova_cookie will store the reserved iova_domain
handle. An RB tree ind
On ARM, MSI write transactions from device upstream to the smmu
are conveyed through the iommu. Therefore target physical addresses
must be mapped and DOMAIN_ATTR_MSI_MAPPING is set to advertise
this requirement on arm-smmu and arm-smmu-v3.
Signed-off-by: Eric Auger
Signed-off-by: Bharat Bhushan
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